SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Interrupt Status Register
The interrupt status regroups all the status of the module internal events that can generate an interrupt.
MMCHS_STAT[31:16] = Error Interrupt Status
MMCHS_STAT[15:0] = Normal Interrupt Status.
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| Instance Name | Physical Address |
|---|---|
| MMCSD0 | 4830 0230h |
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
| RESERVED3 | BADA | CERR | RESERVED2 | TE | ADMAE | ACE | |
| R | R/W | R/W | R | R/W | R/W | R/W | |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | |
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| CLE | DEB | DCRC | DTO | CIE | CEB | CCRC | CTO |
| R | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| ERRI | RESERVED | BSR | OBI | CIRQ | |||
| R | R | R/W | R/W | R | |||
| 0h | 0h | 0h | 0h | 0h | |||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CREM | CINS | BRR | BWR | DMA | BGE | TC | CC |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| 0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 31:30 | RESERVED3 | R | 0h | |
| 29 | BADA | R/W | 0h | Bad access to data space This bit is set automatically to indicate a bad access to buffer when not allowed: -This bit is set during a read access to the data register [MMCSD_DATA] while buffer reads are not allowed [MMCSD_PSTATE[BRE] =0] -This bit is set during a write access to the data register [MMCSD_DATA] while buffer writes are not allowed [MMCSD_STATE[BWE] =0] 1 Bad Access 1 Status is cleared 0 No Interrupt. 0 Status bit unchanged |
| 28 | CERR | R/W | 0h | Card error This bit is set automatically when there is at least one error in a response of type R1, R1b, R6, R5 or R5b. Only bits referenced as type E[error] in status field in the response can set a card status error. An error bit in the response is flagged only if corresponding bit in card status response error MMCSD_CSRE in set. There is no card error detection for autoCMD12 command. The host driver shall read MMCSD_RSP76 register to detect error bits in the command response. 1 Card error 1 Status is cleared 0 No Error 0 Status bit unchanged |
| 27 | RESERVED2 | R | 0h | |
| 26 | TE | R/W | 0h | Tuning Error This bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure [Occurrence of an error during tuning procedure is indicated by Sampling Select]. By detecting Tuning Error, Host Driver needs to abort a command executing and perform tuning. To reset tuning circuit, Sampling Clock shall be set to 0 before executing tuning procedure. The Tuning Error is higher priority than the other error interrupts generated during data transfer. By detecting Tuning Error, the Host Driver should discard data transferred by a current read/write command and retry data transfer after the Host Controller retrieved from tuning circuit error. The bit is set if the lock is lost [but not during the tuning process] or if the lock counter expires without the lock being asserted. If the latter happens, the SW can decide to ignore the interrupt and wait some more for the lock to be set. 1 Error 0 No Error |
| 25 | ADMAE | R/W | 0h | ADMA Error: This bit is set when the Host Controller detects errors during ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the ADMA Error Status Register.In addition, the Host Controller generates this interrupt when it detects invalid descriptor data [Valid=0] at the ST_FDS state. ADMA Error State in the ADMA Error Status indicates that an error occurs in ST_FDS state. The Host Driver may find that Valid bit is not set at the error descriptor. 1 ADMA error 1 Status is cleared 0 No Interrupt. 0 Status bit unchanged |
| 24 | ACE | R/W | 0h | Auto CMD error Auto CMD12 and Auto CMD23 use this error status. This bit is set when detecting that one of the bits D00-D04 in Auto CMD Error Status register has changed from 0 to 1. In case of Auto CMD12, this bit is set to 1, not only when the errors in Auto CMD12 occur but also when Auto CMD12 is not executed due to the previous command error. 1 Auto CMD error 1 Status is cleared 0 No Error. 0 Status bit unchanged |
| 23 | CLE | R | 0h | Reserved. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored. |
| 22 | DEB | R/W | 0h | Data End Bit error This bit is set automatically when detecting a 0 at the end bit position of read data on DAT line or at the end position of the CRC status in write mode. 1 Data end bit error 1 Status is cleared 0 No Error 0 Status bit unchanged |
| 21 | DCRC | R/W | 0h | Data CRC Error This bit is set automatically when there is a CRC16 error in the data phase response following a block read command or if there is a 3-bit CRC status different of a position "010" token during a block write command. 1 Data CRC error 1 Status is cleared 0 No Error. 0 Status bit unchanged |
| 20 | DTO | R/W | 0h | Data timeout error This bit is set automatically according to the following conditions: - busy timeout for R1b, R5b response type - busy timeout after write CRC status - write CRC status timeout - read data timeout 1 Time out 1 Status is cleared 0 No error. 0 Status bit unchanged |
| 19 | CIE | R/W | 0h | Command index error This bit is set automatically when response index differs from corresponding command index previously emitted. It depends on the enable in MMCSD_CMD[CICE] register. 1 Command index error 1 Status is cleared 0 No error. 0 Status bit unchanged |
| 18 | CEB | R/W | 0h | Command end bit error This bit is set automatically when detecting a 0 at the end bit position of a command response. 1 Command end bit error 1 Status is cleared 0 No error. 0 Status bit unchanged |
| 17 | CCRC | R/W | 0h | Command CRC Error This bit is set automatically when there is a CRC7 error in the command response depending on the enable in MMCSD_CMD[CCCE] register. 1 Command CRC error 1 Status is cleared 0 No Error. 0 Status bit unchanged |
| 16 | CTO | R/W | 0h | Command Timeout Error This bit is set automatically when no response is received within 64 clock cycles from the end bit of the command. For commands that reply within 5 clock cycles - the timeout is still detected at 64 clock cycles. 1 Time Out 1 Status is cleared 0 No error 0 Status bit unchanged |
| 15 | ERRI | R | 0h | Error Interrupt If any of the bits in the Error Interrupt Status register [MMCSD_STAT[24:15]] are set, then this bit is set to 1. Therefore the host driver can efficiently test for an error by checking this bit first. Writes to this bit are ignored. 1 Error interrupt event(s) occurred 0 No Interrupt. |
| 14:11 | RESERVED | R | 0h | |
| 10 | BSR | R/W | 0h | Boot status received interrupt This bit is set automatically when MMCSD_CON[BOOT] is set 0x1 or 0x2 and a boot status is received on DAT[0] line. This interrupt is only useful for MMC card. 1 Boot status received interrupt. 1 Status is cleared 0 No Interrupt. 0 Status bit unchanged |
| 9 | OBI | R/W | 0h | Out-Of-Band interrupt This bit is set automatically when MMCSD_CON[OBIE] is set and an Out-of-Band interrupt occurs on OBI pin. The interrupt detection depends on polarity controlled by MMCSD_CON[OBIP]. This interrupt is only useful for MMC card. The Out-of-Band interrupt signal is a system specific feature for future use, this signal is not required for existing specification implementation. 1 Interrupt Out-Of-Band occurs 1 Status is cleared 0 No Out-Of-Band interrupt. 0 Status bit unchanged |
| 8 | CIRQ | R | 0h | Card interrupt This bit is only used for SD and SDIO and CE-ATA cards. In 1-bit mode, interrupt source is asynchronous [can be a source of asynchronous wakeup]. In 4-bit mode, interrupt source is sampled during the interrupt cycle. In CE-ATA mode, interrupt source is detected when the card drives CMD line to zero during one cycle after data transmission end.All modes above are fully exclusive. The controller interrupt must be clear by setting MMCSD_IE[CIRQ] to 0, then the host driver must start the interrupt service with card [clearing card interrupt status] to remove card interrupt source. Otherwise the Controller interrupt will be reasserted as soon as MMCSD_IE[CIRQ] is set to 1. Writes to this bit are ignored. 1 Generate card interrupt 0 No card interrupt |
| 7 | CREM | R/W | 0h | Card removal This bit is set automatically when MMCSD_PSTATE[CINS] changes from 1 to 0. A clear of this bit doesn't effect Card inserted present state [MMCSD_PSTATE[CINS]]. 1 Card removed 1 Status is cleared 0 Card state stable or Debouncing 0 Status bit unchanged |
| 6 | CINS | R/W | 0h | Card insertion This bit is set automatically when MMCSD_PSTATE[CINS] changes from 0 to 1. A clear of this bit doesn't effect Card inserted present state [MMCSD_PSTATE[CINS]]. 1 Card inserted 1 Status is cleared 0 Card state stable or debouncing 0 Status bit unchanged |
| 5 | BRR | R/W | 0h | Buffer read ready This bit is set automatically during a read operation to the card [see class 2 - block oriented read commands] when one block specified by MMCSD_BLK[BLEN] is completely written in the buffer. It indicates that the memory card has filled out the buffer and that the local host needs to empty the buffer by Reading it. Note: If the DMA receive-mode is enabled, this bit is never set; instead a DMA receive request to the main DMA controller of the system is generated. 1 Ready to read buffer 1 Status is cleared 0 Not Ready to read buffer 0 Status bit unchanged |
| 4 | BWR | R/W | 0h | Buffer write ready This bit is set automatically during a write operation to the card [see class 4 - block oriented write command] when the host can write a complete block as specified by MMCSD_BLK[BLEN]. It indicates that the memory card has emptied one block from the buffer and that the local host is able to write one block of data into the buffer. Note: If the DMA transmit mode is enabled, this bit is never set; instead, a DMA transmit request to the main DMA controller of the system is generated. 1 Ready to write buffer 1 Status is cleared 0 Not Ready to write buffer 0 Status bit unchanged |
| 3 | DMA | R/W | 0h | DMA interrupt : This status is set when an interrupt is required in the ADMA instruction and after the data transfer completion. 1 No dma interrupt 1 Status is cleared 0 Dma interrupt detected 0 Status bit unchanged |
| 2 | BGE | R/W | 0h | Block gap event When a stop at block gap is requested [MMCSD_HCTL[SBGR]], this bit is automatically set when transaction is stopped at the block gap during a read or write operation. This event does not occur when the stop at block gap is requested on the last block. In read mode, a 1-to-0 transition of the DAT Line active status [MMCSD_PSTATE[DLA]] between data blocks generates a Block gap event interrupt. 1 Transaction stopped at block gap 1 Status is cleared 0 No block gap event 0 Status bit unchanged |
| 1 | TC | R/W | 0h | Transfer completed This bit is always set when a read/write transfer is completed or between two blocks when the transfer is stopped due to a stop at block gap request [MMCSD_HCTL[SBGR]]. In Read mode: This bit is automatically set on completion of a read transfer [MMCSD_PSTATE[RTA]]. In write mode: This bit is set automatically on completion of the DAT line use [MMCSD_PSTATE[DLA]]. 1 Data transfer complete 1 Status is cleared 0 No transfer complete 0 Status bit unchanged |
| 0 | CC | R/W | 0h | Command complete This bit is set when a 1-to-0 transition occurs in the register command inhibit [MMCSD_PSTATE[CMDI]] If the command is a type for which no response is expected, then the command complete interrupt is generated at the end of the command. A command timeout error [MMCSD_STAT[CTO]] has higher priority than command complete [MMCSD_STAT[CC]]. If a response is expected but none is received, then a command timeout error is detected and signaled instead of the command complete interrupt. 1 Command complete 1 Status is cleared 0 No Command complete 0 Status bit unchanged |