SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.15.2.23 MMC_ISE Register

15.2.23.1 MMC_ISE Register (Offset = 238h) [reset = 0h]

Interrupt Signal Enable Register

This register allows to enable/disable the module internal sources of status, on an event-by-event basis.

MMCHS_ISE[31:16] = Error Interrupt Signal Enable
MMCHS_ISE[15:0] = Normal Interrupt Signal Enable.

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Table 5-1808 Instance Table

Instance Name	Physical Address
MMCSD0	4830 0238h

Figure 5-892 MMC_ISE Name Register

31	30	29	28	27	26	25	24
RESERVED3		BADA_SIGEN	CERR_SIGEN	RESERVED2	TE_SIGEN	ADMAE_SIGEN	ACE_SIGEN
R		R/W	R/W	R	R/W	R/W	R/W
0h		0h	0h	0h	0h	0h	0h
23	22	21	20	19	18	17	16
CLE	DEB_SIGEN	DCRC_SIGEN	DTO_SIGEN	CIE_SIGEN	CEB_SIGEN	CCRC_SIGEN	CTO_SIGEN
R	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h
15	14	13	12	11	10	9	8
NULL	RESERVED				BSR_SIGEN	OBI_SIGEN	CIRQ_SIGEN
R	R				R/W	R/W	R/W
0h	0h				0h	0h	0h
7	6	5	4	3	2	1	0
CREM_SIGEN	CINS_SIGEN	BRR_SIGEN	BWR_SIGEN	DMA_SIGEN	BGE_SIGEN	TC_SIGEN	CC_SIGEN
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h

Table 5-1809 MMC_ISE Register Field Descriptions

Bit	Field	Type	Reset	Description
31:30	RESERVED3	R	0h
29	BADA_SIGEN	R/W	0h	Bad access to data space Signal Enable 1 Enabled 0 Masked
28	CERR_SIGEN	R/W	0h	Card Error Interrupt Signal Enable 1 Enabled 0 Masked
27	RESERVED2	R	0h
26	TE_SIGEN	R/W	0h	Tuning Error Signal Enable 1 Enabled 0 Masked
25	ADMAE_SIGEN	R/W	0h	ADMA Error Signal Enable 1 Enabled 0 Masked
24	ACE_SIGEN	R/W	0h	Auto CMD Error Signal Enable 1 Enabled 0 Masked
23	CLE	R	0h	Reserved bit. Current limit error is not supported. These bits are initialized to zero, and writes to them are ignored.
22	DEB_SIGEN	R/W	0h	Data End Bit Error Signal Enable 1 Enabled 0 Masked
21	DCRC_SIGEN	R/W	0h	Data CRC Error Signal Enable 1 Enabled 0 Masked
20	DTO_SIGEN	R/W	0h	Data Timeout Error Signal Enable 1 Enabled 0 Masked
19	CIE_SIGEN	R/W	0h	Command Index Error Signal Enable 1 Enabled 0 Masked
18	CEB_SIGEN	R/W	0h	Command End Bit Error Signal Enable 1 Enabled 0 Masked
17	CCRC_SIGEN	R/W	0h	Command CRC Error Signal Enable 1 Enabled 0 Masked
16	CTO_SIGEN	R/W	0h	Command timeout Error Signal Enable 1 Enabled 0 Masked
15	NULL	R	0h	Fixed to 0 The host driver shall control error interrupts using the Error Interrupt Signal Enable register. Writes to this bit are ignored
14:11	RESERVED	R	0h
10	BSR_SIGEN	R/W	0h	Boot Status Signal Enable A write to this register when MMCSD_CON[BOOT_ACK] is set to 0x0 is ignored. 1 Enabled 0 Masked
9	OBI_SIGEN	R/W	0h	Out-Of-Band Interrupt Signal Enable A write to this register when MMCSD_CON[OBIE] is set to '0' is ignored. 1 Enabled 0 Masked
8	CIRQ_SIGEN	R/W	0h	Card Interrupt Signal Enable 1 Enabled 0 Masked
7	CREM_SIGEN	R/W	0h	Card Removal Signal Enable 1 Enabled 0 Masked
6	CINS_SIGEN	R/W	0h	Card Insertion Signal Enable 1 Enabled 0 Masked
5	BRR_SIGEN	R/W	0h	Buffer Read Ready Signal Enable 1 Enabled 0 Masked
4	BWR_SIGEN	R/W	0h	Buffer Write Ready Signal Enable 1 Enabled 0 Masked
3	DMA_SIGEN	R/W	0h	DMA Interrupt Signal Enable 1 Enabled 0 Masked
2	BGE_SIGEN	R/W	0h	Black Gap Event Signal Enable 1 Enabled 0 Masked
1	TC_SIGEN	R/W	0h	Transfer Completed Status Enable 1 Enabled 0 Masked
0	CC_SIGEN	R/W	0h	Command Complete Status Enable 1 Enabled 0 Masked