SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.15.2.25 MMC_CAPA Register

15.2.25.1 MMC_CAPA Register (Offset = 240h) [reset = E10080h]

Capabilities Register

This register lists the capabilities of the MMC/SD/SDIO host controller.

Table 5-1812 Instance Table

Instance Name	Physical Address
MMCSD0	4830 0240h

Figure 5-894 MMC_CAPA Name Register

31	30	29	28	27	26	25	24
RESERVED4		AIS	BIT64	RESERVED3	VS18	VS30	VS33
R		R	R	R	R/W	R/W	R/W
0h		0h	0h	0h	0h	0h	0h
23	22	21	20	19	18	17	16
SRS	DS	HSS	RESERVED2	AD2S	RESERVED1	MBL
R	R	R	R	R	R	R
1h	1h	1h	0h	0h	0h	1h
15	14	13	12	11	10	9	8
BCF
R
0h
7	6	5	4	3	2	1	0
TCU	RESERVED	TCF
R	R	R
1h	0h	0h

Table 5-1813 MMC_CAPA Register Field Descriptions

Bit	Field	Type	Reset	Description
31:30	RESERVED4	R	0h
29	AIS	R	0h	Asynchronous Interrupt Support Refer to SDIO Specification Version 3.00 about asynchronous interrupt. 1 Asynchronous Interrupt Supported 0 Asynchronous Interrupt Not Supported
28	BIT64	R	0h	64 Bit System Bus Support Setting 1 to this bit indicates that the Host Controller supports 64-bit address descriptor mode and is connected to 64-bit address system bus. 1 64 bit System bus address 0 32 bit System bus address
27	RESERVED3	R	0h
26	VS18	R/W	0h	Voltage support 1.8V Initialization of this register [via a write access to this register] depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset [via RESETN signal] 1 1.8V Supported 1 1.8V Supported 0 1.8V Not supported 0 1.8V Not Supported
25	VS30	R/W	0h	Voltage support 3.0V Initialization of this register [via a write access to this register] depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset [via RESETN signal] 1 3.0V Supported 1 3.0V Supported 0 3.0V Not supported 0 3.0V Not Supported
24	VS33	R/W	0h	Voltage support 3.3V Initialization of this register [via a write access to this register] depends on the system capabilities. The host driver shall not modify this register after the initilaization. This register is only reinitialized by a hard reset [via RESETN signal] 1 3.3V Supported 1 3.3V Supported 0 3.3V Not supported 0 3.3V Not Supported
23	SRS	R	1h	Suspend/Resume support [SDIO cards only] This bit indicates whether the host controller supports Suspend/Resume functionality. 1 The Host controller supports Suspend/Resume functionality. 0 The Host controller does not Suspend/Resume functionality.
22	DS	R	1h	DMA support This bit indicates that the Host Controller is able to use DMA to transfer data between system memory and the Host Controller directly. 1 DMA Supported 0 DMA Not Supported
21	HSS	R	1h	High speed support This bit indicates that the host controller supports high speed operations and can supply an up-to maximum card frequency. 1 High Speed Supported 0 High Speed Not Supported
20	RESERVED2	R	0h
19	AD2S	R	0h	ADMA2 Support This bit indicates whether the Host Controller is capable of using ADMA2. It depends on setting of generic parameter MADMA_EN 1 ADMA2 Supported 0 ADMA2 not Supported
18	RESERVED1	R	0h
17:16	MBL	R	1h	Maximum block length This value indicates the maximum block size that the host driver can read and write to the buffer in the host controller. This value depends on definition of generic parameter with a max value of 2048bytes. The host controller supports 512 bytes and 1024bytes block transfers. 2 2048 bytes 1 1024 bytes 0 512 bytes
15:8	BCF	R	0h	Base Clock Frequency For SD Clock This value indicates the base [maximum] clock frequency for the SD Clock. 8-bit Base Clock Frequency This mode is supported by the Host Controller Version 3.00. Unit values are 1MHz. The supported clock range is 10MHz to 255MHz. FFh : 255MHz .... : ....... 02h: 2MHz 01h: 1MHz 00h: Get information via another method If the real frequency is 16.5MHz, the lager value shall be set 00010001b [17MHz] because the Host Driver use this value to calculate the clock divider value [Refer to the SDCLK Frequency Select in the Clock Control register.] and it shall not exceed upper limit of the SD Clock frequency. If these bits are all 0, the Host System has to get information via another method. 0 The value indicating the base (maximum) frequency for the output clock provided to the card is system dependent and is not available in this register. Get the information via another method.
7	TCU	R	1h	Timeout clock unit This bit shows the unit of base clock frequency used to detect Data Timeout Error [MMCSD_STAT[DTO]]. 1 MHz 0 KHz
6	RESERVED	R	0h
5:0	TCF	R	0h	Timeout clock frequency The timeout clock frequency is used to detect Data Timeout Error [MMCSD_STAT[DTO]]. 0 The timeout clock frequency depends on the frequency of the clock provided to the card. The value of the timeout clock frequency is not available in this register.