SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Interrupt Enable Set Register 0
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Instance Name | Physical Address |
---|---|
R5SS0 | 5300 0080h |
R5SS1 | 5300 4080h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | CPU0_KS_VIM_RAMECC_ENABLE_SET | B1TCM0_BANK1_ENABLE_SET | B1TCM0_BANK0_ENABLE_SET | B0TCM0_BANK1_ENABLE_SET | |||
NONE | R/W1TS | R/W1TS | R/W1TS | R/W1TS | |||
0h | 0h | 0h | 0h | 0h | |||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
B0TCM0_BANK0_ENABLE_SET | ATCM0_BANK1_ENABLE_SET | ATCM0_BANK0_ENABLE_SET | CPU0_DDATA_RAM7_ENABLE_SET | CPU0_DDATA_RAM6_ENABLE_SET | CPU0_DDATA_RAM5_ENABLE_SET | CPU0_DDATA_RAM4_ENABLE_SET | CPU0_DDATA_RAM3_ENABLE_SET |
R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CPU0_DDATA_RAM2_ENABLE_SET | CPU0_DDATA_RAM1_ENABLE_SET | CPU0_DDATA_RAM0_ENABLE_SET | CPU0_DDIRTY_RAM_ENABLE_SET | CPU0_DTAG_RAM3_ENABLE_SET | CPU0_DTAG_RAM2_ENABLE_SET | CPU0_DTAG_RAM1_ENABLE_SET | CPU0_DTAG_RAM0_ENABLE_SET |
R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CPU0_IDATA_BANK3_ENABLE_SET | CPU0_IDATA_BANK2_ENABLE_SET | CPU0_IDATA_BANK1_ENABLE_SET | CPU0_IDATA_BANK0_ENABLE_SET | CPU0_ITAG_RAM3_ENABLE_SET | CPU0_ITAG_RAM2_ENABLE_SET | CPU0_ITAG_RAM1_ENABLE_SET | CPU0_ITAG_RAM0_ENABLE_SET |
R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:28 | RESERVED | NONE | 0h | Reserved |
27 | CPU0_KS_VIM_RAMECC_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_ks_vim_ramecc_pend |
26 | B1TCM0_BANK1_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for b1tcm0_bank1_pend |
25 | B1TCM0_BANK0_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for b1tcm0_bank0_pend |
24 | B0TCM0_BANK1_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for b0tcm0_bank1_pend |
23 | B0TCM0_BANK0_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for b0tcm0_bank0_pend |
22 | ATCM0_BANK1_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for atcm0_bank1_pend |
21 | ATCM0_BANK0_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for atcm0_bank0_pend |
20 | CPU0_DDATA_RAM7_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_ddata_ram7_pend |
19 | CPU0_DDATA_RAM6_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_ddata_ram6_pend |
18 | CPU0_DDATA_RAM5_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_ddata_ram5_pend |
17 | CPU0_DDATA_RAM4_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_ddata_ram4_pend |
16 | CPU0_DDATA_RAM3_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_ddata_ram3_pend |
15 | CPU0_DDATA_RAM2_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_ddata_ram2_pend |
14 | CPU0_DDATA_RAM1_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_ddata_ram1_pend |
13 | CPU0_DDATA_RAM0_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_ddata_ram0_pend |
12 | CPU0_DDIRTY_RAM_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_ddirty_ram_pend |
11 | CPU0_DTAG_RAM3_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_dtag_ram3_pend |
10 | CPU0_DTAG_RAM2_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_dtag_ram2_pend |
9 | CPU0_DTAG_RAM1_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_dtag_ram1_pend |
8 | CPU0_DTAG_RAM0_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_dtag_ram0_pend |
7 | CPU0_IDATA_BANK3_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_idata_bank3_pend |
6 | CPU0_IDATA_BANK2_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_idata_bank2_pend |
5 | CPU0_IDATA_BANK1_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_idata_bank1_pend |
4 | CPU0_IDATA_BANK0_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_idata_bank0_pend |
3 | CPU0_ITAG_RAM3_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_itag_ram3_pend |
2 | CPU0_ITAG_RAM2_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_itag_ram2_pend |
1 | CPU0_ITAG_RAM1_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_itag_ram1_pend |
0 | CPU0_ITAG_RAM0_ENABLE_SET | R/W1TS | 0h | Interrupt Enable Set Register for cpu0_itag_ram0_pend |