SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

1.2.78.1 ECC_AGG_CORE0_AGGR_STATUS_CLR Register (Offset = 20Ch) [reset = 0h]

AGGR interrupt status clear Register.

Table 4-174 Instance Table

Instance Name	Physical Address
R5SS0	5300 020Ch
R5SS1	5300 420Ch

Figure 4-78 ECC_AGG_CORE0_AGGR_STATUS_CLR Name Register

Table 4-175 ECC_AGG_CORE0_AGGR_STATUS_CLR Register Field Descriptions

Bit	Field	Type	Reset	Description
31:4	RESERVED	NONE	0h	Reserved
3:2	TIMEOUT	R/WD	0h	2'b00 - No timeout errors have occurred 2'b01 - 1 timeout erro has occurred 2'b10 - 2 timeout error has occurred 2'b11 - 3 or more timeout errors have occurred A write of a non-zero value to this register decrements that many from the timeout fields. If the resulting written value is non zero, then the pending level interrupt stays asserted. A new pulse interrupt will nto be asserted, you must write the eoi register for that to occur. If you write a value more than the counter value the result will be zero.
1:0	PARITY	R/WD	0h	2'b00 - No parity errors have occurred 2'b01 - 1 parity error has occurred 2'b10 - 2 parity error has occurred 2'b11 - 3 or more parity error have occurred A write of a non-zero value to this register decrements that many from the parity fields. If the resulting written value is non zero, then the pending level interrupt stays asserted. A new pulse interrupt will nto be asserted, you must write the eoi register for that to occur. If you write a value more than the counter value the result will be zero.