SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

1.2.28.1 CPSW_MDIO_USER_GROUP_USER_ACCESS_REG_K Register (Offset = F80h) [reset = 0h]

MDIO User Access Register

Offset = Base + (k * 8h); where k = 0 to 1d

Table 5-56 Instance Table

Instance Name	Physical Address
CPSW0	5280 0F80h + formula

Figure 5-28 CPSW_MDIO_USER_GROUP_USER_ACCESS_REG_K Name Register

Table 5-57 CPSW_MDIO_USER_GROUP_USER_ACCESS_REG_K Register Field Descriptions

Bit	Field	Type	Reset	Description
31	GO	R/W	0h	Go. Writing a 1 to this bit causes the MDIO state machine to perform an MDIO access when it is convenient for it to do so, this is not an instantaneous process. Writing a 0 to this bit has no effect. This bit is write able only if the MDIO state machine is enabled. This bit will self clear when the requested access has been completed. Any writes to the MDIOUserAccess0 register are blocked when the go bit is 1. If byte access is being used, the go bit should be written last.
30	WRITE	R/W	0h	Write enable. Setting this bit to a 1 causes the MDIO transaction to be a register write, otherwise it is a register read.
29	ACK	R/W	0h	Acknowledge. This bit is set if the PHY acknowledged the read transaction.
28:26	RESERVED	NONE	0h	Reserved
25:21	REGADR	R/W	0h	Register address. This field specifies the PHY register to be accessed for this transaction in clause 22 mode or the MMD value in clause 45 mode.
20:16	PHYADR	R/W	0h	PHY address. This field specifies the PHY to be accessed for this transaction.
15:0	DATA	R/W	0h	User data. The data value read from or to be written to the specified PHY register.