SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Core 3 Misc Interrupt Enable Register
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Instance Name | Physical Address |
---|---|
CPSW0 | 5280 18CCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DED_PEND_EN | SEC_PEND_EN | EVNT_PEND_EN | STAT_PEND_EN | HOST_PEND_EN | MDIO_LINKINT_EN | MDIO_USERINT_EN |
NONE | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:7 | RESERVED | NONE | 0h | Reserved |
6 | DED_PEND_EN | R/W | 0h | Core 3 MISC DED Memory Protect Error Interrupt Enable - enabled to generate an interrupt on C3_Misc_PULSE |
5 | SEC_PEND_EN | R/W | 0h | Core 3 MISC SEC Memory Protect Error Interrupt Enable - enabled to generate an interrupt on C3_Misc_PULSE |
4 | EVNT_PEND_EN | R/W | 0h | Core 3 MISC CPTS Event Interrupt Enable - enabled to generate an interrupt on C3_Misc_PULSE |
3 | STAT_PEND_EN | R/W | 0h | Core 3 MISC Statistics Interrupt Enable - Logical OR of all port statistics bits (bits n downto 0) - enabled to generate an interrupt on C3_Misc_PULSE |
2 | HOST_PEND_EN | R/W | 0h | Core 3 MISC Host Interrupt Enable - enabled to generate an interrupt on C3_Misc_PULSE |
1 | MDIO_LINKINT_EN | R/W | 0h | Core 3 MISC MDIO linkint - Logical OR of bits 1 and 0 - enabled to generate an interrupt on C3_Misc_PULSE |
0 | MDIO_USERINT_EN | R/W | 0h | Core 3 MISC_MDIO userint interrupt enable - Logical OR of bits 1 and 0 - enabled to generate an interrupt on C3_Misc_PULSE |