SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Misc Interrupt Status Register - Set bits in this register indicate that an enabled interrupt is asserted
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Instance Name | Physical Address |
---|---|
CPSW0 | 5280 18DCh |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | DED_PEND | SEC_PEND | EVNT_PEND | STAT_PEND | HOST_PEND | MDIO_LINKINT | MDIO_USERINT |
NONE | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:7 | RESERVED | NONE | 0h | Reserved |
6 | DED_PEND | R/W | 0h | Core 3 MISC DED Memory Protect Error Interrupt |
5 | SEC_PEND | R/W | 0h | Core 3 MISC SEC Memory Protect Error Interrupt |
4 | EVNT_PEND | R/W | 0h | Core 3 MISC CPTS Event Interrupt |
3 | STAT_PEND | R/W | 0h | Core 3 MISC Statistics Interrupt - Logical OR of bits n downto 0 |
2 | HOST_PEND | R/W | 0h | Core 3 MISC Host Interrupt Enable |
1 | MDIO_LINKINT | R/W | 0h | Core 3 MISC MDIO linkint - Logical OR of bits 1 and 0 |
0 | MDIO_USERINT | R/W | 0h | Core 3 MISC_MDIO userint interrupt - Logical OR of bits 1 and 0 |