SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

1.2.133.1 CPSW_NC_ETH_MAC_PN_EEE_STATUS_REG_K Register (Offset = 22038h) [reset = 62h]

Enet Port N EEE status

Offset = Base + (k * 1000h); where k = 0 to 1d

Table 5-266 Instance Table

Instance Name	Physical Address
CPSW0	5282 2038h + formula

Figure 5-133 CPSW_NC_ETH_MAC_PN_EEE_STATUS_REG_K Name Register

Table 5-267 CPSW_NC_ETH_MAC_PN_EEE_STATUS_REG_K Register Field Descriptions

Bit	Field	Type	Reset	Description
31:7	RESERVED	NONE	0h	Reserved
6	TX_FIFO_EMPTY	R	1h	Transmit FIFO (switch egress) is empty - contains no packets
5	RX_FIFO_EMPTY	R	1h	Receive FIFO (switch ingress) is empty - contains no packets
4	TX_FIFO_HOLD	R	0h	Transmit FIFO hold - asserted in the LPI state and during the LPI2WAKE count time
3	TX_WAKE	R	0h	Transmit wakeup - asserted in the transmit LPI2WAKE count time
2	TX_LPI	R	0h	Transmit LPI state - asserted when the port 0 transmit is in the LPI state
1	RX_LPI	R	1h	Receive LPI state - asserted when the port 0 receive is in the LPI state
0	WAIT_IDLE2LPI	R	0h	CPPI port 0 wait idle to LPI - asserted when port 0 is counting the IDLE2LPI time