SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
CPDMA Soft Reset Register
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Instance Name | Physical Address |
---|---|
CPSW0 | 5283 401Ch |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED | SOFT_RESET | ||||||
NONE | R/W | ||||||
0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:1 | RESERVED | NONE | 0h | Reserved |
0 | SOFT_RESET | R/W | 0h | Software reset - Writing a one to this bit causes the entire CPSW logic to be reset. Software reset occurs when the DMA Controllers are in an idle state to avoid locking up the VBUSP bus. After writing a one to this bit, it may be polled to determine if the reset has occurred. If a one is read, the reset has not yet occurred. If a zero is read then reset has occurred. |