SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

5.1.2.181 CPSW_NC_CPDMA_REGS_CONTROL_REG Register

1.2.181.1 CPSW_NC_CPDMA_REGS_CONTROL_REG Register (Offset = 34020h) [reset = 0h]

CPDMA Control Register

Table 5-362 Instance Table

Instance Name	Physical Address
CPSW0	5283 4020h

Figure 5-181 CPSW_NC_CPDMA_REGS_CONTROL_REG Name Register

31	30	29	28	27	26	25	24
RESERVED
NONE
0h
23	22	21	20	19	18	17	16
RESERVED
NONE
0h
15	14	13	12	11	10	9	8
RESERVED							FH_OWNERSHIP
NONE							R/W
0h							0h
7	6	5	4	3	2	1	0
TH_CH_OVERRIDE	TH_TS_ENCAP	TH_VLAN_ENCAP	TH_CEF	CMD_IDLE	TH_OFFLEN_BLOCK	TH_OWNERSHIP	FH_PTYPE
R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
0h	0h	0h	0h	0h	0h	0h	0h

Table 5-363 CPSW_NC_CPDMA_REGS_CONTROL_REG Register Field Descriptions

Bit	Field	Type	Reset	Description
31:9	RESERVED	NONE	0h	Reserved
8	FH_OWNERSHIP	R/W	0h	CPDMA FHost Ownership Write Bit Value. 0 - The CPDMA writes the FHost buffer descriptor ownership bit to zero at the end of packet processing as specified in CPPI 3.0. 1 - The CPDMA writes the FHost buffer descriptor ownership bit to one at the end of packet processing. Users who do not use the ownership mechanism can use this mode to preclude the necessity of software having to set this bit each time the buffer descriptor is used. Software must set this bit when building the packet chain.
7	TH_CH_OVERRIDE	R/W	0h	CPDMA THost Channel Classification Match Override Enable 0 - The THost channel is not overridden with the ALE classification match. 1 - The THOST channel is overridden with the lower 3-bits of the ALE classification match value (if a classification match occurred).
6	TH_TS_ENCAP	R/W	0h	CPDMA THost Packet Timestamp Encapsulation 0 - THost packets do not contain a 64-bit timestamp 1 - THost packets contain a 64-bit timestamp prepended to the packet data (32-bit lsword first).
5	TH_VLAN_ENCAP	R/W	0h	CPDMA THost Packet VLAN Encapsulation 0 - THost packets are not VLAN encapsulated 1 - THost packets are VLAN encapsulated
4	TH_CEF	R/W	0h	CPDMA THost Copy Error Frames Enable - Enables THost DMA overrun frames to be transferred to memory (up to the point of buffer overrun). The overrun error bit will be set in the frame EOP buffer descriptor. Overrun frame data will be filtered when thost_cef is not set. THost frames with other error bits set are not affected by this bit. This is related only to frames that overrun on the THost DMA due to buffer limitations. 0 - Frames containing overrun errors are filtered. 1 - Frames containing overrun errors are transferred to memory.
3	CMD_IDLE	R/W	0h	CPDMA Command Idle 0 - Idle not commanded 1 - Idle Commanded (read idle in CPDMA_Status register)
2	TH_OFFLEN_BLOCK	R/W	0h	CPDMA THost Offset/Length word write block 0 - Do not block the DMA writes to the THost buffer descriptor offset/buffer length word. The offset/buffer length word is written as specified in CPPI 3.0. 1 - Block all CPDMA DMA controller writes to the THost buffer descriptor offset/buffer length words during CPPI packet processing. When this bit is set, the CPDMA will never write the third word to any THost buffer descriptor.
1	TH_OWNERSHIP	R/W	0h	CPDMA THost Ownership Write Bit Value 0 - The CPDMA writes the THost buffer descriptor ownership bit to zero at the end of packet processing as specified in CPPI 3.0. 1 - The CPDMA writes the THost buffer descriptor ownership bit to one at the end of packet processing. Users who do not use the ownership mechanism can use this mode to preclude the necessity of software having to set this bit each time the buffer descriptor is used. Software must set this bit when building the packet chain.
0	FH_PTYPE	R/W	0h	CPDMA FHost Queue Priority Type 0 - The queue uses a round robin scheme to select the next channel. 1 - The queue uses a fixed (channel 7 highest priority) priority scheme to select the next channel.