SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
CPDMA THost Interrupt Masked SET
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Instance Name | Physical Address |
---|---|
CPSW0 | 5283 40A8h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED | |||||||
NONE | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
TH7_THRESH_PEND_MASKED_SET | TH6_THRESH_PEND_MASKED_SET | TH5_THRESH_PEND_MASKED_SET | TH4_THRESH_PEND_MASKED_SET | TH3_THRESH_PEND_MASKED_SET | TH2_THRESH_PEND_MASKED_SET | TH1_THRESH_PEND_MASKED_SET | TH0_THRESH_PEND_MASKED_SET |
R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
TH7_PEND_MASKED_SET | TH6_PEND_MASKED_SET | TH5_PEND_MASKED_SET | TH4_PEND_MASKED_SET | TH3_PEND_MASKED_SET | TH2_PEND_MASKED_SET | TH1_PEND_MASKED_SET | TH0_PEND_MASKED_SET |
R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:16 | RESERVED | NONE | 0h | Reserved |
15 | TH7_THRESH_PEND_MASKED_SET | R/W1TS | 0h | CPDMA THost Channel 7 Threshold Interrupt Pending SET - write one to enable interrupt |
14 | TH6_THRESH_PEND_MASKED_SET | R/W1TS | 0h | CPDMA THost Channel 6 Threshold Interrupt Pending SET - write one to enable interrupt |
13 | TH5_THRESH_PEND_MASKED_SET | R/W1TS | 0h | CPDMA THost Channel 5 Threshold Interrupt Pending SET - write one to enable interrupt |
12 | TH4_THRESH_PEND_MASKED_SET | R/W1TS | 0h | CPDMA THost Channel 4 Threshold Interrupt Pending SET - write one to enable interrupt |
11 | TH3_THRESH_PEND_MASKED_SET | R/W1TS | 0h | CPDMA THost Channel 3 Threshold Interrupt Pending SET - write one to enable interrupt |
10 | TH2_THRESH_PEND_MASKED_SET | R/W1TS | 0h | CPDMA THost Channel 2 Threshold Interrupt Pending SET - write one to enable interrupt |
9 | TH1_THRESH_PEND_MASKED_SET | R/W1TS | 0h | CPDMA THost Channel 1 Threshold Interrupt Pending SET - write one to enable interrupt |
8 | TH0_THRESH_PEND_MASKED_SET | R/W1TS | 0h | CPDMA THost Channel 0 Threshold Interrupt Pending SET - write one to enable interrupt |
7 | TH7_PEND_MASKED_SET | R/W1TS | 0h | CPDMA THost Channel 7 Interrupt Pending SET - write one to enable interrupt |
6 | TH6_PEND_MASKED_SET | R/W1TS | 0h | CPDMA THost Channel 6 Interrupt Pending SET - write one to enable interrupt |
5 | TH5_PEND_MASKED_SET | R/W1TS | 0h | CPDMA THost Channel 5 Interrupt Pending SET - write one to enable interrupt |
4 | TH4_PEND_MASKED_SET | R/W1TS | 0h | CPDMA THost Channel 4 Interrupt Pending SET - write one to enable interrupt |
3 | TH3_PEND_MASKED_SET | R/W1TS | 0h | CPDMA THost Channel 3 Interrupt Pending SET - write one to enable interrupt |
2 | TH2_PEND_MASKED_SET | R/W1TS | 0h | CPDMA THost Channel 2 Interrupt Pending SET - write one to enable interrupt |
1 | TH1_PEND_MASKED_SET | R/W1TS | 0h | CPDMA THost Channel 1 Interrupt Pending SET - write one to enable interrupt |
0 | TH0_PEND_MASKED_SET | R/W1TS | 0h | CPDMA THost Channel 0 Interrupt Pending SET - write one to enable interrupt |