SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

4.2.2.207 ICSSM_PR1_ICSS_UART_UART_SLV_MCR Register

2.2.207.1 ICSSM_PR1_ICSS_UART_UART_SLV_MCR Register (Offset = 10h) [reset = 0h]

Modem Control Register (MCR)
The modem control register provides the ability to enable/disable the autoflow functions, and enable/disable the loopback function for diagnostic purposes.

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Table 4-835 Instance Table

Instance Name	Physical Address
ICSSM0	4802 8010h

Figure 4-401 ICSSM_PR1_ICSS_UART_UART_SLV_MCR Name Register

31	30	29	28	27	26	25	24
RESERVED
NONE
0h
23	22	21	20	19	18	17	16
RESERVED
NONE
0h
15	14	13	12	11	10	9	8
RESERVED
NONE
0h
7	6	5	4	3	2	1	0
RESERVED		AFE	LOOP	OUT2	OUT1	RTS	RESERVED
NONE		R/W	R/W	R/W	R/W	R/W	R/W
0h		0h	0h	0h	0h	0h	0h

Table 4-836 ICSSM_PR1_ICSS_UART_UART_SLV_MCR Register Field Descriptions

Bit	Field	Type	Reset	Description
31:6	RESERVED	NONE	0h	Reserved
5	AFE	R/W	0h	Autoflow control enable. Autoflow control allows the UARTn_RTS and UARTn_CTS signals to provide handshaking between UARTs during data transfer. When AFE = 1, the RTS bit determines the autoflow control enabled. Note that all UARTs do not support this feature, see your device-specific data manual for supported features. If this feature is not available, this bit is reserved and should be cleared to 0. 1 Autoflow control is enabled: -When RTS = 0, UARTnCTS is only enabled -When RTS = 1, UARTn_RTS and UARTn_CTS are enabled 0 Autoflow control is disabled.
4	LOOP	R/W	0h	Loop back mode enable. LOOP is used for the diagnostic testing using the loop back feature. 1 Loop back mode is enabled. When LOOP is set, the following occur: -The UARTn_TXD signal is set high. -The UARTn_RXD pin is disconnected -The output of the transmitter shift register (TSR) is lopped back in to the receiver shift register (RSR) input. 0 Loop back mode is disabled.
3	OUT2	R/W	0h	Out2 Bit
2	OUT1	R/W	0h	Out1 Bit
1	RTS	R/W	0h	RTS control. When AFE = 1, the RTS bit determines the autoflow control enabled. Note that all UARTs do not support this feature, see your device-specific data manual for supported features. If this feature is not available, this bit is reserved and should be cleared to 0. 1 UARTn_RTS and UARTn_CTS are enabled. 0 UARTn_RTS is disabled, UARTn_CTS is only enabled.
0	RESERVED	R/W	0h	Reserved