SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

4.2.2.216 ICSSM_PR1_ICSS_UART_UART_SLV_THR Register

2.2.216.1 ICSSM_PR1_ICSS_UART_UART_SLV_THR Register (Offset = 0h) [reset = 0h]

The transmitter holding register (THR) (write only)
The UART transmitter section consists of a transmitter hold register (THR) and a transmitter shift register (TSR). When the UART is in the FIFO mode, THR is a 16-byte FIFO. Transmitter section control is a function of the line control register (LCR).
THR receives data from the internal data bus and when TSR is idle, the UART moves the data from THR to TSR. The UART serializes the data in TSR and transmits the data on the TX pin. In the non-FIFO mode, if THR is empty and the THR empty (THRE) interrupt is enabled (ETBEI = 1 in IER), an interrupt is generated. This interrupt is cleared when a character is loaded into THR or the interrupt identification register (IIR) is read. In the FIFO mode, the interrupt is generated when the transmitter FIFO is empty, and it is cleared when at least one byte is loaded into the FIFO or IIR is read.

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Table 4-853 Instance Table

Instance Name	Physical Address
ICSSM0	4802 8000h

Figure 4-410 ICSSM_PR1_ICSS_UART_UART_SLV_THR Name Register

31	30	29	28	27	26	25	24
RESERVED
NONE
0h
23	22	21	20	19	18	17	16
RESERVED
NONE
0h
15	14	13	12	11	10	9	8
RESERVED
NONE
0h
7	6	5	4	3	2	1	0
DATA
W
0h

Table 4-854 ICSSM_PR1_ICSS_UART_UART_SLV_THR Register Field Descriptions

Bit	Field	Type	Reset	Description
31:8	RESERVED	NONE	0h	Reserved
7:0	DATA	W	0h	Data to transmit