SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Counter Phase Offset Value Register.
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Instance Name | Physical Address |
---|---|
ECAP0 | 5024 0004h |
ECAP1 | 5024 1004h |
ECAP2 | 5024 2004h |
ECAP3 | 5024 3004h |
ECAP4 | 5024 4004h |
ECAP5 | 5024 5004h |
ECAP6 | 5024 6004h |
ECAP7 | 5024 7004h |
ECAP8 | 5024 8004h |
ECAP9 | 5024 9004h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CTRPHS | |||||||
R/W | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CTRPHS | |||||||
R/W | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CTRPHS | |||||||
R/W | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CTRPHS | |||||||
R/W | |||||||
0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:0 | CTRPHS | R/W | 0h | Counter phase value register that can be programmed for phase lag/lead. This register CTRPHS is loaded into TSCTR upon either a SYNCI event or S/W force via a control bit. Used to achieve phase control synchronization with respect to other eCAP and EPWM time-bases. This register is not applicable in HR mode. |