SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

6.2.7.1 ECAP_ECCTL0 Register (Offset = 24h) [reset = FFh]

Capture Control Register 0

Table 3-474 Instance Table

Figure 3-229 ECAP_ECCTL0 Name Register

Table 3-475 ECAP_ECCTL0 Register Field Descriptions

Bit	Field	Type	Reset	Description
31:18	RESERVED_2	R	0h	Reserved
17:16	SOCEVTSEL	R/W	0h	ADC SOC event select Capture Mode: 00b[R/W] = SOC trigger source is CEVT1 01b[R/W] = SOC trigger source is CEVT2 10b[R/W] = SOC trigger source is CEVT3 11b[R/W] = SOC trigger source is CEVT4 APWM Mode: 00b[R/W] = SOC trigger interrupt source is period match 01b[R/W] = SOC trigger interrupt source is compare match 10b[R/W] = SOC trigger interrupt source is period match or compare match 11b[R/W] = Disabled
15:12	QUALPRD	R/W	0h	Qual period to filter out noise on input signals being monitored, Not applicable for HR mode. 0x0 : Bypass 0x1 : pulses of with 1 cycle or less will be filtered out 0x2 : pulses of with 2 cycles or less will be filtered out .... 0xF : pulses of with 15 cycles or less will be filtered out
11:8	RESERVED_1	R	0h	Reserved
7:0	INPUTSEL	R/W	FFh	Capture input source select bits 0x0 capture input is ECAPxINPUT[0] 0x1 capture input is ECAPxINPUT[1] 0x2 capture input is ECAPxINPUT[2] ... 0xFF capture input is ECAPxINPUT[256]