SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
High-Res Calibration Interrupt Clear Register.
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Instance Name | Physical Address |
---|---|
ECAP0 | 5024 0050h |
ECAP1 | 5024 1050h |
ECAP2 | 5024 2050h |
ECAP3 | 5024 3050h |
ECAP4 | 5024 4050h |
ECAP5 | 5024 5050h |
ECAP6 | 5024 6050h |
ECAP7 | 5024 7050h |
ECAP8 | 5024 8050h |
ECAP9 | 5024 9050h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED_1 | |||||||
R | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
RESERVED_1 | |||||||
R | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED_1 | |||||||
R | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | CALPRDCHKSTS | CALIBDONE | CALIBINT | ||||
R | R/W1TC | R/W1TC | R/W1TC | ||||
0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:3 | RESERVED_1 | R | 0h | Reserved |
2 | CALPRDCHKSTS | R/W1TC | 0h | Clear Calibration period check status Flag Bit: 1 Clears the CALPRDCHKSTS flag register bit. 0 No effect. Note: H/W has priority over CPU writes if the user tries to clear a flag bit and an event occurs on the same cycle that tries to set the flag for the selected bit. |
1 | CALIBDONE | R/W1TC | 0h | Clear Calibration Done Interrupt Flag Bit: 1 Clears the CALIBDONE interrupt flag register bit. 0 No effect. Note: H/W has priority over CPU writes if the user tries to clear a flag bit and an event occurs on the same cycle that tries to set the flag for the selected bit. |
0 | CALIBINT | R/W1TC | 0h | Clear Global calibration Interrupt Flag 1 Clears the Global interrupt flag and enables further interrupts to be generated if any of the event flags are set. 0 No effect. |