SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

3.6.2.25 ECAP_HRDEBUGCTL Register

6.2.25.1 ECAP_HRDEBUGCTL Register (Offset = 74h) [reset = 0h]

High-Res Debug control register.

Table 3-510 Instance Table

Instance Name	Physical Address
ECAP0	5024 0074h
ECAP1	5024 1074h
ECAP2	5024 2074h
ECAP3	5024 3074h
ECAP4	5024 4074h
ECAP5	5024 5074h
ECAP6	5024 6074h
ECAP7	5024 7074h
ECAP8	5024 8074h
ECAP9	5024 9074h

Figure 3-247 ECAP_HRDEBUGCTL Name Register

31	30	29	28	27	26	25	24
RESERVED_3
R
0h
23	22	21	20	19	18	17	16
RESERVED_3
R
0h
15	14	13	12	11	10	9	8
RESERVED_3				OBSERVE_SRC_SEL
R				R/W
0h				0h
7	6	5	4	3	2	1	0
RESERVED_2		CALIB_INPUT_SEL		RESERVED_1	CAPIN_MMAP_SOURCE	DELAYRESETDLINE	DISABLEINVSEL
R		R/W		R	R/W	R/W	R/W
0h		0h		0h	0h	0h	0h

Table 3-511 ECAP_HRDEBUGCTL Register Field Descriptions

Bit	Field	Type	Reset	Description
31:12	RESERVED_3	R	0h	Reserved
11:8	OBSERVE_SRC_SEL	R/W	0h	Select bits for selecting source for OBSERVE1 and OBSERVE2 registers 1000:HROUTH and HROUTL will read HR1OUT 1001:HROUTH and HROUTL will read HR2OUT 1010:HROUTH and HROUTL will read Capture Delayline 1 OBS1 1011:HROUTH and HROUTL will read Capture Delayline 2 OBS1 1100:HROUTH and HROUTL will read Capture Delayline 1 OBS2 1101:HROUTH and HROUTL will read Capture Delayline 2 OBS2
7:6	RESERVED_2	R	0h	Reserved
5:4	CALIB_INPUT_SEL	R/W	0h	Select bit for calibration input, can be used to get fault coverage using these inputs 00 CAPIN is one of 128 inputs selected by INPUTSEL 01 CAPIN is connected to CAPIN_MEMMAP_SOURCE 10 CAPIN is internally generated signal waveform with 8HRCLK cycle high and 8HRCLK cycle low, used for linearity check of capture delay line 1 11 CAPIN is internally generated signal waveform with 8HRCLK cycle high and 8HRCLK cycle low, delayed by half HRCLK, used for linearity check of capture delay line 2
3	RESERVED_1	R	0h	Reserved
2	CAPIN_MMAP_SOURCE	R/W	0h	Memory mapped CAPIN source Note : select CALIN source first, it may happen that you may see interrupt if MMAP source is different from current value of CAPIN. This is debug feature hence no additional HW is necessary to prevent this.
1	DELAYRESETDLINE	R/W	0h	Controls the reset delayline timing 0 reset is forced on next falling edge of HRCLK [1/2 cycle after capture] 1 reset is applied a cycle later [1 1/2 cycles after capture]
0	DISABLEINVSEL	R/W	0h	Disable INVSEL Logic: 0 State machine controls inversion on input signal 1 CAPIN signal propagated into delay line without inversion, this means only rising edges can be measured