SPRUJ42 User guide

SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1

PRODUCTION DATA

8.2.27.1 EQEP_QEPSRCSEL Register (Offset = 6Ch) [reset = 0h]

QEP Source Select Register.

Table 3-990 Instance Table

Figure 3-465 EQEP_QEPSRCSEL Name Register

Table 3-991 EQEP_QEPSRCSEL Register Field Descriptions

Bit	Field	Type	Reset	Description
31:29	RESERVED_4	R	0h	Reserved
28:24	QEPSSEL	R/W	0h	QEP Strobe source select: 0x0 : Reserved 0x1 : Device Pin 0x2 : PWMXBAR.Out[0] 0x3 : PWMXBAR.Out[1] ... 0x1F : PWMXBAR.Out[29] Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running.
23:21	RESERVED_3	R	0h	Reserved
20:16	QEPISEL	R/W	0h	QEP Index source select: 0x0 : Reserved 0x1 : Device Pin 0x2 : PWMXBAR.Out[0] 0x3 : PWMXBAR.Out[1] ... 0x1F : PWMXBAR.Out[29] Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running.
15:13	RESERVED_2	R	0h	Reserved
12:8	QEPBSEL	R/W	0h	QEPB source select: 0x0 : Reserved 0x1 : Device Pin 0x2 : PWMXBAR.Out[0] 0x3 : PWMXBAR.Out[1] ... 0x1F : PWMXBAR.Out[29] Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running.
7:5	RESERVED_1	R	0h	Reserved
4:0	QEPASEL	R/W	0h	QEPA source select: 0x0 : Reserved 0x1 : Device Pin 0x2 : PWMXBAR.Out[0] 0x3 : PWMXBAR.Out[1] ... 0x1F : PWMXBAR.Out[29] Note: eQEP needs to be disabled before configuring these bits as it can lead to unexpected behavior if eQEP is running.