SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Time Base Control Register 2
Return to Summary Table
Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 0002h |
EPWM0_G1 | 5004 0002h |
EPWM0_G2 | 5008 0002h |
EPWM0_G3 | 500C 0002h |
EPWM1_G0 | 5000 1002h |
EPWM1_G1 | 5004 1002h |
EPWM1_G2 | 5008 1002h |
EPWM1_G3 | 500C 1002h |
EPWM2_G0 | 5000 2002h |
EPWM2_G1 | 5004 2002h |
EPWM2_G2 | 5008 2002h |
EPWM2_G3 | 500C 2002h |
EPWM3_G0 | 5000 3002h |
EPWM3_G1 | 5004 3002h |
EPWM3_G2 | 5008 3002h |
EPWM3_G3 | 500C 3002h |
EPWM4_G0 | 5000 4002h |
EPWM4_G1 | 5004 4002h |
EPWM4_G2 | 5008 4002h |
EPWM4_G3 | 500C 4002h |
EPWM5_G0 | 5000 5002h |
EPWM5_G1 | 5004 5002h |
EPWM5_G2 | 5008 5002h |
EPWM5_G3 | 500C 5002h |
EPWM6_G0 | 5000 6002h |
EPWM6_G1 | 5004 6002h |
EPWM6_G2 | 5008 6002h |
EPWM6_G3 | 500C 6002h |
EPWM7_G0 | 5000 7002h |
EPWM7_G1 | 5004 7002h |
EPWM7_G2 | 5008 7002h |
EPWM7_G3 | 500C 7002h |
EPWM8_G0 | 5000 8002h |
EPWM8_G1 | 5004 8002h |
EPWM8_G2 | 5008 8002h |
EPWM8_G3 | 500C 8002h |
EPWM9_G0 | 5000 9002h |
EPWM9_G1 | 5004 9002h |
EPWM9_G2 | 5008 9002h |
EPWM9_G3 | 500C 9002h |
EPWM10_G0 | 5000 A002h |
EPWM10_G1 | 5004 A002h |
EPWM10_G2 | 5008 A002h |
EPWM10_G3 | 500C A002h |
EPWM11_G0 | 5000 B002h |
EPWM11_G1 | 5004 B002h |
EPWM11_G2 | 5008 B002h |
EPWM11_G3 | 500C B002h |
EPWM12_G0 | 5000 C002h |
EPWM12_G1 | 5004 C002h |
EPWM12_G2 | 5008 C002h |
EPWM12_G3 | 500C C002h |
EPWM13_G0 | 5000 D002h |
EPWM13_G1 | 5004 D002h |
EPWM13_G2 | 5008 D002h |
EPWM13_G3 | 500C D002h |
EPWM14_G0 | 5000 E002h |
EPWM14_G1 | 5004 E002h |
EPWM14_G2 | 5008 E002h |
EPWM14_G3 | 500C E002h |
EPWM15_G0 | 5000 F002h |
EPWM15_G1 | 5004 F002h |
EPWM15_G2 | 5008 F002h |
EPWM15_G3 | 500C F002h |
EPWM16_G0 | 5001 0002h |
EPWM16_G1 | 5005 0002h |
EPWM16_G2 | 5009 0002h |
EPWM16_G3 | 500D 0002h |
EPWM17_G0 | 5001 1002h |
EPWM17_G1 | 5005 1002h |
EPWM17_G2 | 5009 1002h |
EPWM17_G3 | 500D 1002h |
EPWM18_G0 | 5001 2002h |
EPWM18_G1 | 5005 2002h |
EPWM18_G2 | 5009 2002h |
EPWM18_G3 | 500D 2002h |
EPWM19_G0 | 5001 3002h |
EPWM19_G1 | 5005 3002h |
EPWM19_G2 | 5009 3002h |
EPWM19_G3 | 500D 3002h |
EPWM20_G0 | 5001 4002h |
EPWM20_G1 | 5005 4002h |
EPWM20_G2 | 5009 4002h |
EPWM20_G3 | 500D 4002h |
EPWM21_G0 | 5001 5002h |
EPWM21_G1 | 5005 5002h |
EPWM21_G2 | 5009 5002h |
EPWM21_G3 | 500D 5002h |
EPWM22_G0 | 5001 6002h |
EPWM22_G1 | 5005 6002h |
EPWM22_G2 | 5009 6002h |
EPWM22_G3 | 500D 6002h |
EPWM23_G0 | 5001 7002h |
EPWM23_G1 | 5005 7002h |
EPWM23_G2 | 5009 7002h |
EPWM23_G3 | 500D 7002h |
EPWM24_G0 | 5001 8002h |
EPWM24_G1 | 5005 8002h |
EPWM24_G2 | 5009 8002h |
EPWM24_G3 | 500D 8002h |
EPWM25_G0 | 5001 9002h |
EPWM25_G1 | 5005 9002h |
EPWM25_G2 | 5009 9002h |
EPWM25_G3 | 500D 9002h |
EPWM26_G0 | 5001 A002h |
EPWM26_G1 | 5005 A002h |
EPWM26_G2 | 5009 A002h |
EPWM26_G3 | 500D A002h |
EPWM27_G0 | 5001 B002h |
EPWM27_G1 | 5005 B002h |
EPWM27_G2 | 5009 B002h |
EPWM27_G3 | 500D B002h |
EPWM28_G0 | 5001 C002h |
EPWM28_G1 | 5005 C002h |
EPWM28_G2 | 5009 C002h |
EPWM28_G3 | 500D C002h |
EPWM29_G0 | 5001 D002h |
EPWM29_G1 | 5005 D002h |
EPWM29_G2 | 5009 D002h |
EPWM29_G3 | 500D D002h |
EPWM30_G0 | 5001 E002h |
EPWM30_G1 | 5005 E002h |
EPWM30_G2 | 5009 E002h |
EPWM30_G3 | 500D E002h |
EPWM31_G0 | 5001 F002h |
EPWM31_G1 | 5005 F002h |
EPWM31_G2 | 5009 F002h |
EPWM31_G3 | 500D F002h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
PRDLDSYNC | RESERVED_3 | RESERVED_2 | |||||
R/W | R | R | |||||
0h | 0h | 0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
OSHTSYNC | OSHTSYNCMODE | SELFCLRTRREM | RESERVED_1 | ||||
R/W1TS | R/W | R/W | R | ||||
0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:14 | PRDLDSYNC | R/W | 0h | Shadow to Active Period Register Load on SYNC event 00:Shadow to Active Load of TBPRD occurs only when TBCTR = 0 [same as legacy]. 01:Shadow to Active Load of TBPRD occurs both when TBCTR = 0 and when SYNC occurs. 10:Shadow to Active Load of TBPRD occurs only when a SYNC is received. 11:Reserved Note: This bit selection is valid only if TBCTL[PRDLD]=0. |
13:12 | RESERVED_3 | R | 0h | Reserved |
11:8 | RESERVED_2 | R | 0h | Reserved |
7 | OSHTSYNC | R/W1TS | 0h | Oneshot sync bit 0:Writing a '0' has no effect. 1:Allow one sync pulse to propogate. |
6 | OSHTSYNCMODE | R/W | 0h | Oneshot sync enable bit 0:Oneshot sync mode disabled 1:Oneshot sync mode enabled |
5 | SELFCLRTRREM | R/W | 0h | Loop back sync pulse to enable self sync operation 0:Self clear function of TRREM disabled. 1:Self clear function of TRREM enabled |
4:0 | RESERVED_1 | R | 0h | Reserved |