SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
EPWMxSYNCOUT Source Enable Register.
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Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 000Ch |
EPWM0_G1 | 5004 000Ch |
EPWM0_G2 | 5008 000Ch |
EPWM0_G3 | 500C 000Ch |
EPWM1_G0 | 5000 100Ch |
EPWM1_G1 | 5004 100Ch |
EPWM1_G2 | 5008 100Ch |
EPWM1_G3 | 500C 100Ch |
EPWM2_G0 | 5000 200Ch |
EPWM2_G1 | 5004 200Ch |
EPWM2_G2 | 5008 200Ch |
EPWM2_G3 | 500C 200Ch |
EPWM3_G0 | 5000 300Ch |
EPWM3_G1 | 5004 300Ch |
EPWM3_G2 | 5008 300Ch |
EPWM3_G3 | 500C 300Ch |
EPWM4_G0 | 5000 400Ch |
EPWM4_G1 | 5004 400Ch |
EPWM4_G2 | 5008 400Ch |
EPWM4_G3 | 500C 400Ch |
EPWM5_G0 | 5000 500Ch |
EPWM5_G1 | 5004 500Ch |
EPWM5_G2 | 5008 500Ch |
EPWM5_G3 | 500C 500Ch |
EPWM6_G0 | 5000 600Ch |
EPWM6_G1 | 5004 600Ch |
EPWM6_G2 | 5008 600Ch |
EPWM6_G3 | 500C 600Ch |
EPWM7_G0 | 5000 700Ch |
EPWM7_G1 | 5004 700Ch |
EPWM7_G2 | 5008 700Ch |
EPWM7_G3 | 500C 700Ch |
EPWM8_G0 | 5000 800Ch |
EPWM8_G1 | 5004 800Ch |
EPWM8_G2 | 5008 800Ch |
EPWM8_G3 | 500C 800Ch |
EPWM9_G0 | 5000 900Ch |
EPWM9_G1 | 5004 900Ch |
EPWM9_G2 | 5008 900Ch |
EPWM9_G3 | 500C 900Ch |
EPWM10_G0 | 5000 A00Ch |
EPWM10_G1 | 5004 A00Ch |
EPWM10_G2 | 5008 A00Ch |
EPWM10_G3 | 500C A00Ch |
EPWM11_G0 | 5000 B00Ch |
EPWM11_G1 | 5004 B00Ch |
EPWM11_G2 | 5008 B00Ch |
EPWM11_G3 | 500C B00Ch |
EPWM12_G0 | 5000 C00Ch |
EPWM12_G1 | 5004 C00Ch |
EPWM12_G2 | 5008 C00Ch |
EPWM12_G3 | 500C C00Ch |
EPWM13_G0 | 5000 D00Ch |
EPWM13_G1 | 5004 D00Ch |
EPWM13_G2 | 5008 D00Ch |
EPWM13_G3 | 500C D00Ch |
EPWM14_G0 | 5000 E00Ch |
EPWM14_G1 | 5004 E00Ch |
EPWM14_G2 | 5008 E00Ch |
EPWM14_G3 | 500C E00Ch |
EPWM15_G0 | 5000 F00Ch |
EPWM15_G1 | 5004 F00Ch |
EPWM15_G2 | 5008 F00Ch |
EPWM15_G3 | 500C F00Ch |
EPWM16_G0 | 5001 000Ch |
EPWM16_G1 | 5005 000Ch |
EPWM16_G2 | 5009 000Ch |
EPWM16_G3 | 500D 000Ch |
EPWM17_G0 | 5001 100Ch |
EPWM17_G1 | 5005 100Ch |
EPWM17_G2 | 5009 100Ch |
EPWM17_G3 | 500D 100Ch |
EPWM18_G0 | 5001 200Ch |
EPWM18_G1 | 5005 200Ch |
EPWM18_G2 | 5009 200Ch |
EPWM18_G3 | 500D 200Ch |
EPWM19_G0 | 5001 300Ch |
EPWM19_G1 | 5005 300Ch |
EPWM19_G2 | 5009 300Ch |
EPWM19_G3 | 500D 300Ch |
EPWM20_G0 | 5001 400Ch |
EPWM20_G1 | 5005 400Ch |
EPWM20_G2 | 5009 400Ch |
EPWM20_G3 | 500D 400Ch |
EPWM21_G0 | 5001 500Ch |
EPWM21_G1 | 5005 500Ch |
EPWM21_G2 | 5009 500Ch |
EPWM21_G3 | 500D 500Ch |
EPWM22_G0 | 5001 600Ch |
EPWM22_G1 | 5005 600Ch |
EPWM22_G2 | 5009 600Ch |
EPWM22_G3 | 500D 600Ch |
EPWM23_G0 | 5001 700Ch |
EPWM23_G1 | 5005 700Ch |
EPWM23_G2 | 5009 700Ch |
EPWM23_G3 | 500D 700Ch |
EPWM24_G0 | 5001 800Ch |
EPWM24_G1 | 5005 800Ch |
EPWM24_G2 | 5009 800Ch |
EPWM24_G3 | 500D 800Ch |
EPWM25_G0 | 5001 900Ch |
EPWM25_G1 | 5005 900Ch |
EPWM25_G2 | 5009 900Ch |
EPWM25_G3 | 500D 900Ch |
EPWM26_G0 | 5001 A00Ch |
EPWM26_G1 | 5005 A00Ch |
EPWM26_G2 | 5009 A00Ch |
EPWM26_G3 | 500D A00Ch |
EPWM27_G0 | 5001 B00Ch |
EPWM27_G1 | 5005 B00Ch |
EPWM27_G2 | 5009 B00Ch |
EPWM27_G3 | 500D B00Ch |
EPWM28_G0 | 5001 C00Ch |
EPWM28_G1 | 5005 C00Ch |
EPWM28_G2 | 5009 C00Ch |
EPWM28_G3 | 500D C00Ch |
EPWM29_G0 | 5001 D00Ch |
EPWM29_G1 | 5005 D00Ch |
EPWM29_G2 | 5009 D00Ch |
EPWM29_G3 | 500D D00Ch |
EPWM30_G0 | 5001 E00Ch |
EPWM30_G1 | 5005 E00Ch |
EPWM30_G2 | 5009 E00Ch |
EPWM30_G3 | 500D E00Ch |
EPWM31_G0 | 5001 F00Ch |
EPWM31_G1 | 5005 F00Ch |
EPWM31_G2 | 5009 F00Ch |
EPWM31_G3 | 500D F00Ch |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED_2 | |||||||
R | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | DCBEVT1EN | DCAEVT1EN | CMPDEN | CMPCEN | CMPBEN | ZEROEN | SWEN |
R | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 1h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | RESERVED_2 | R | 0h | Reserved |
7 | RESERVED_1 | R | 0h | Reserved |
6 | DCBEVT1EN | R/W | 0h | This bit enables the DCBEVT1.sync event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a DCBEVT1.sync event |
5 | DCAEVT1EN | R/W | 0h | This bit enables the DCAEVT1.sync event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon a DCAEVT1.sync event |
4 | CMPDEN | R/W | 0h | This bit enables the TBCTR = CMPD event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare D event [TBCTR = CMPD] |
3 | CMPCEN | R/W | 0h | This bit enables the TBCTR = CMPC event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare C event [TBCTR = CMPC] |
2 | CMPBEN | R/W | 0h | This bit enables the TBCTR = CMPB event to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period upon a time-base counter equal to counter compare B event [TBCTR = CMPB] |
1 | ZEROEN | R/W | 0h | This bit enables the TBCTR = 0x0000 event to set the EPWMxSYNCOUT signal. 0 Disabled 1 The EPWMxSYNCOUT signal is pulsed for one PWM clock period upon the value of TBCTR changing to 0x0000 |
0 | SWEN | R/W | 1h | This bit enables the TBCTL.SWFSYNC bit to set the EPWMxSYNCO signal. 0 Disabled 1 The EPWMxSYNCO signal is pulsed for one PWM clock period when the TBCTL.SWFSYNC bit is set |