SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Valley Counter Config Register.
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Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 0032h |
EPWM0_G1 | 5004 0032h |
EPWM0_G2 | 5008 0032h |
EPWM0_G3 | 500C 0032h |
EPWM1_G0 | 5000 1032h |
EPWM1_G1 | 5004 1032h |
EPWM1_G2 | 5008 1032h |
EPWM1_G3 | 500C 1032h |
EPWM2_G0 | 5000 2032h |
EPWM2_G1 | 5004 2032h |
EPWM2_G2 | 5008 2032h |
EPWM2_G3 | 500C 2032h |
EPWM3_G0 | 5000 3032h |
EPWM3_G1 | 5004 3032h |
EPWM3_G2 | 5008 3032h |
EPWM3_G3 | 500C 3032h |
EPWM4_G0 | 5000 4032h |
EPWM4_G1 | 5004 4032h |
EPWM4_G2 | 5008 4032h |
EPWM4_G3 | 500C 4032h |
EPWM5_G0 | 5000 5032h |
EPWM5_G1 | 5004 5032h |
EPWM5_G2 | 5008 5032h |
EPWM5_G3 | 500C 5032h |
EPWM6_G0 | 5000 6032h |
EPWM6_G1 | 5004 6032h |
EPWM6_G2 | 5008 6032h |
EPWM6_G3 | 500C 6032h |
EPWM7_G0 | 5000 7032h |
EPWM7_G1 | 5004 7032h |
EPWM7_G2 | 5008 7032h |
EPWM7_G3 | 500C 7032h |
EPWM8_G0 | 5000 8032h |
EPWM8_G1 | 5004 8032h |
EPWM8_G2 | 5008 8032h |
EPWM8_G3 | 500C 8032h |
EPWM9_G0 | 5000 9032h |
EPWM9_G1 | 5004 9032h |
EPWM9_G2 | 5008 9032h |
EPWM9_G3 | 500C 9032h |
EPWM10_G0 | 5000 A032h |
EPWM10_G1 | 5004 A032h |
EPWM10_G2 | 5008 A032h |
EPWM10_G3 | 500C A032h |
EPWM11_G0 | 5000 B032h |
EPWM11_G1 | 5004 B032h |
EPWM11_G2 | 5008 B032h |
EPWM11_G3 | 500C B032h |
EPWM12_G0 | 5000 C032h |
EPWM12_G1 | 5004 C032h |
EPWM12_G2 | 5008 C032h |
EPWM12_G3 | 500C C032h |
EPWM13_G0 | 5000 D032h |
EPWM13_G1 | 5004 D032h |
EPWM13_G2 | 5008 D032h |
EPWM13_G3 | 500C D032h |
EPWM14_G0 | 5000 E032h |
EPWM14_G1 | 5004 E032h |
EPWM14_G2 | 5008 E032h |
EPWM14_G3 | 500C E032h |
EPWM15_G0 | 5000 F032h |
EPWM15_G1 | 5004 F032h |
EPWM15_G2 | 5008 F032h |
EPWM15_G3 | 500C F032h |
EPWM16_G0 | 5001 0032h |
EPWM16_G1 | 5005 0032h |
EPWM16_G2 | 5009 0032h |
EPWM16_G3 | 500D 0032h |
EPWM17_G0 | 5001 1032h |
EPWM17_G1 | 5005 1032h |
EPWM17_G2 | 5009 1032h |
EPWM17_G3 | 500D 1032h |
EPWM18_G0 | 5001 2032h |
EPWM18_G1 | 5005 2032h |
EPWM18_G2 | 5009 2032h |
EPWM18_G3 | 500D 2032h |
EPWM19_G0 | 5001 3032h |
EPWM19_G1 | 5005 3032h |
EPWM19_G2 | 5009 3032h |
EPWM19_G3 | 500D 3032h |
EPWM20_G0 | 5001 4032h |
EPWM20_G1 | 5005 4032h |
EPWM20_G2 | 5009 4032h |
EPWM20_G3 | 500D 4032h |
EPWM21_G0 | 5001 5032h |
EPWM21_G1 | 5005 5032h |
EPWM21_G2 | 5009 5032h |
EPWM21_G3 | 500D 5032h |
EPWM22_G0 | 5001 6032h |
EPWM22_G1 | 5005 6032h |
EPWM22_G2 | 5009 6032h |
EPWM22_G3 | 500D 6032h |
EPWM23_G0 | 5001 7032h |
EPWM23_G1 | 5005 7032h |
EPWM23_G2 | 5009 7032h |
EPWM23_G3 | 500D 7032h |
EPWM24_G0 | 5001 8032h |
EPWM24_G1 | 5005 8032h |
EPWM24_G2 | 5009 8032h |
EPWM24_G3 | 500D 8032h |
EPWM25_G0 | 5001 9032h |
EPWM25_G1 | 5005 9032h |
EPWM25_G2 | 5009 9032h |
EPWM25_G3 | 500D 9032h |
EPWM26_G0 | 5001 A032h |
EPWM26_G1 | 5005 A032h |
EPWM26_G2 | 5009 A032h |
EPWM26_G3 | 500D A032h |
EPWM27_G0 | 5001 B032h |
EPWM27_G1 | 5005 B032h |
EPWM27_G2 | 5009 B032h |
EPWM27_G3 | 500D B032h |
EPWM28_G0 | 5001 C032h |
EPWM28_G1 | 5005 C032h |
EPWM28_G2 | 5009 C032h |
EPWM28_G3 | 500D C032h |
EPWM29_G0 | 5001 D032h |
EPWM29_G1 | 5005 D032h |
EPWM29_G2 | 5009 D032h |
EPWM29_G3 | 500D D032h |
EPWM30_G0 | 5001 E032h |
EPWM30_G1 | 5005 E032h |
EPWM30_G2 | 5009 E032h |
EPWM30_G3 | 500D E032h |
EPWM31_G0 | 5001 F032h |
EPWM31_G1 | 5005 F032h |
EPWM31_G2 | 5009 F032h |
EPWM31_G3 | 500D F032h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
STOPEDGESTS | RESERVED_2 | STOPEDGE | |||||
R | R | R/W | |||||
0h | 0h | 0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
STARTEDGESTS | RESERVED_1 | STARTEDGE | |||||
R | R | R/W | |||||
0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | STOPEDGESTS | R | 0h | Stop Edge Status Bit 0:Stop edge has not occurred 1:Stop edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STOPEDGE occurs. Note:This bit is reset by the occurrence of the trigger pulse selected through VCAPCTL[TRIGSEL] |
14:12 | RESERVED_2 | R | 0h | Reserved |
11:8 | STOPEDGE | R/W | 0h | Counter Stop Edge Selection Once the counter operation is armed, upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would stop counting upon the occurrence of chosen number of events thorough this bit field. Stop counting on occurrence of: 0000 Do not stop 0001 1st edge 0010 2nd edge 0011 3rd edge ... 1111 15th edge |
7 | STARTEDGESTS | R | 0h | Start Edge Status Bit 0:Start edge has not occurred 1:Start edge occurred Note: This bit is set only after the trigger sequence is armed [upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL]] and STARTEDGE occurs. Note:This bit is reset by the occurrence of the trigger pulse selected through VCAPCTL[TRIGSEL] |
6:4 | RESERVED_1 | R | 0h | Reserved |
3:0 | STARTEDGE | R/W | 0h | Counter Start Edge Selection Once the counter operation is armed, upon occurrence of trigger pulse selected through VCAPCTL[TRIGSEL] pulse - valley counter would start counting upon the occurrence of chosen number of events thorough this bit field. Start counting on occurrence of 0000 Do not start 0001 1st edge 0010 2nd edge 0011 3rd edge ... 1111 15th edge |