SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
HRPWM Configuration 2 Register
This register is only accessible on EPWM modules with HRPWM capabilities. Only 16 bit accesses are allowed for this register. Debugger access in 32 bit mode may display incorrect values.
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Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 004Eh |
EPWM0_G1 | 5004 004Eh |
EPWM0_G2 | 5008 004Eh |
EPWM0_G3 | 500C 004Eh |
EPWM1_G0 | 5000 104Eh |
EPWM1_G1 | 5004 104Eh |
EPWM1_G2 | 5008 104Eh |
EPWM1_G3 | 500C 104Eh |
EPWM2_G0 | 5000 204Eh |
EPWM2_G1 | 5004 204Eh |
EPWM2_G2 | 5008 204Eh |
EPWM2_G3 | 500C 204Eh |
EPWM3_G0 | 5000 304Eh |
EPWM3_G1 | 5004 304Eh |
EPWM3_G2 | 5008 304Eh |
EPWM3_G3 | 500C 304Eh |
EPWM4_G0 | 5000 404Eh |
EPWM4_G1 | 5004 404Eh |
EPWM4_G2 | 5008 404Eh |
EPWM4_G3 | 500C 404Eh |
EPWM5_G0 | 5000 504Eh |
EPWM5_G1 | 5004 504Eh |
EPWM5_G2 | 5008 504Eh |
EPWM5_G3 | 500C 504Eh |
EPWM6_G0 | 5000 604Eh |
EPWM6_G1 | 5004 604Eh |
EPWM6_G2 | 5008 604Eh |
EPWM6_G3 | 500C 604Eh |
EPWM7_G0 | 5000 704Eh |
EPWM7_G1 | 5004 704Eh |
EPWM7_G2 | 5008 704Eh |
EPWM7_G3 | 500C 704Eh |
EPWM8_G0 | 5000 804Eh |
EPWM8_G1 | 5004 804Eh |
EPWM8_G2 | 5008 804Eh |
EPWM8_G3 | 500C 804Eh |
EPWM9_G0 | 5000 904Eh |
EPWM9_G1 | 5004 904Eh |
EPWM9_G2 | 5008 904Eh |
EPWM9_G3 | 500C 904Eh |
EPWM10_G0 | 5000 A04Eh |
EPWM10_G1 | 5004 A04Eh |
EPWM10_G2 | 5008 A04Eh |
EPWM10_G3 | 500C A04Eh |
EPWM11_G0 | 5000 B04Eh |
EPWM11_G1 | 5004 B04Eh |
EPWM11_G2 | 5008 B04Eh |
EPWM11_G3 | 500C B04Eh |
EPWM12_G0 | 5000 C04Eh |
EPWM12_G1 | 5004 C04Eh |
EPWM12_G2 | 5008 C04Eh |
EPWM12_G3 | 500C C04Eh |
EPWM13_G0 | 5000 D04Eh |
EPWM13_G1 | 5004 D04Eh |
EPWM13_G2 | 5008 D04Eh |
EPWM13_G3 | 500C D04Eh |
EPWM14_G0 | 5000 E04Eh |
EPWM14_G1 | 5004 E04Eh |
EPWM14_G2 | 5008 E04Eh |
EPWM14_G3 | 500C E04Eh |
EPWM15_G0 | 5000 F04Eh |
EPWM15_G1 | 5004 F04Eh |
EPWM15_G2 | 5008 F04Eh |
EPWM15_G3 | 500C F04Eh |
EPWM16_G0 | 5001 004Eh |
EPWM16_G1 | 5005 004Eh |
EPWM16_G2 | 5009 004Eh |
EPWM16_G3 | 500D 004Eh |
EPWM17_G0 | 5001 104Eh |
EPWM17_G1 | 5005 104Eh |
EPWM17_G2 | 5009 104Eh |
EPWM17_G3 | 500D 104Eh |
EPWM18_G0 | 5001 204Eh |
EPWM18_G1 | 5005 204Eh |
EPWM18_G2 | 5009 204Eh |
EPWM18_G3 | 500D 204Eh |
EPWM19_G0 | 5001 304Eh |
EPWM19_G1 | 5005 304Eh |
EPWM19_G2 | 5009 304Eh |
EPWM19_G3 | 500D 304Eh |
EPWM20_G0 | 5001 404Eh |
EPWM20_G1 | 5005 404Eh |
EPWM20_G2 | 5009 404Eh |
EPWM20_G3 | 500D 404Eh |
EPWM21_G0 | 5001 504Eh |
EPWM21_G1 | 5005 504Eh |
EPWM21_G2 | 5009 504Eh |
EPWM21_G3 | 500D 504Eh |
EPWM22_G0 | 5001 604Eh |
EPWM22_G1 | 5005 604Eh |
EPWM22_G2 | 5009 604Eh |
EPWM22_G3 | 500D 604Eh |
EPWM23_G0 | 5001 704Eh |
EPWM23_G1 | 5005 704Eh |
EPWM23_G2 | 5009 704Eh |
EPWM23_G3 | 500D 704Eh |
EPWM24_G0 | 5001 804Eh |
EPWM24_G1 | 5005 804Eh |
EPWM24_G2 | 5009 804Eh |
EPWM24_G3 | 500D 804Eh |
EPWM25_G0 | 5001 904Eh |
EPWM25_G1 | 5005 904Eh |
EPWM25_G2 | 5009 904Eh |
EPWM25_G3 | 500D 904Eh |
EPWM26_G0 | 5001 A04Eh |
EPWM26_G1 | 5005 A04Eh |
EPWM26_G2 | 5009 A04Eh |
EPWM26_G3 | 500D A04Eh |
EPWM27_G0 | 5001 B04Eh |
EPWM27_G1 | 5005 B04Eh |
EPWM27_G2 | 5009 B04Eh |
EPWM27_G3 | 500D B04Eh |
EPWM28_G0 | 5001 C04Eh |
EPWM28_G1 | 5005 C04Eh |
EPWM28_G2 | 5009 C04Eh |
EPWM28_G3 | 500D C04Eh |
EPWM29_G0 | 5001 D04Eh |
EPWM29_G1 | 5005 D04Eh |
EPWM29_G2 | 5009 D04Eh |
EPWM29_G3 | 500D D04Eh |
EPWM30_G0 | 5001 E04Eh |
EPWM30_G1 | 5005 E04Eh |
EPWM30_G2 | 5009 E04Eh |
EPWM30_G3 | 500D E04Eh |
EPWM31_G0 | 5001 F04Eh |
EPWM31_G1 | 5005 F04Eh |
EPWM31_G2 | 5009 F04Eh |
EPWM31_G3 | 500D F04Eh |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
NOBYPASS | DELLOADFRC | RESERVED_1 | |||||
R/W | R/W1TS | R | |||||
0h | 0h | 0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | CTLMODEDBFED | CTLMODEDBRED | EDGMODEDB | ||||
R | R/W | R/W | R/W | ||||
0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15 | NOBYPASS | R/W | 0h | No Bypass Delay Line Update Bit: For internal test purposes, this bit disables the 1 SYSCLK cycle bypass before delay line is updated. |
14 | DELLOADFRC | R/W1TS | 0h | Delay Line Load Software Force: For internal test purposes, software force generates a pulse which forces a delay line update [similar to PRD_eq/CNT_zero strobe]. |
13:6 | RESERVED_1 | R | 0h | Reserved |
5:4 | CTLMODEDBFED | R/W | 0h | Shadow Mode Bit - selection should match DBCTL[LOADFEDMODE] Selects the time event that loads the DBFEDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10 Load on either CTR = Zero or CTR = PRD 11 Reserved |
3:2 | CTLMODEDBRED | R/W | 0h | Shadow Mode Bit - selection should match DBCTL[LOADREDMODE] Selects the time event that loads the DBREDHR shadow value into the active register. 00 Load on CTR = Zero: Time-base counter equal to zero [TBCTR = 0x0000] 01 Load on CTR = PRD: Time-base counter equal to period [TBCTR = TBPRD] 10 Load on either CTR = Zero or CTR = PRD 11 Reserved |
1:0 | EDGMODEDB | R/W | 0h | Edge Mode Bits Selects the edge of the PWM that is controlled by the micro-edge position [MEP] logic: 00 HRPWM capability is disabled [default on reset] 01 MEP control of rising edge [DBREDHR] 10 MEP control of falling edge [DBFEDHR] 11 MEP control of both edges [rising edge of DBREDHR or falling edge of DBFEDHR ] |