SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Counter Compare A Register .
Return to Summary Table
Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 00D4h |
EPWM0_G1 | 5004 00D4h |
EPWM0_G2 | 5008 00D4h |
EPWM0_G3 | 500C 00D4h |
EPWM1_G0 | 5000 10D4h |
EPWM1_G1 | 5004 10D4h |
EPWM1_G2 | 5008 10D4h |
EPWM1_G3 | 500C 10D4h |
EPWM2_G0 | 5000 20D4h |
EPWM2_G1 | 5004 20D4h |
EPWM2_G2 | 5008 20D4h |
EPWM2_G3 | 500C 20D4h |
EPWM3_G0 | 5000 30D4h |
EPWM3_G1 | 5004 30D4h |
EPWM3_G2 | 5008 30D4h |
EPWM3_G3 | 500C 30D4h |
EPWM4_G0 | 5000 40D4h |
EPWM4_G1 | 5004 40D4h |
EPWM4_G2 | 5008 40D4h |
EPWM4_G3 | 500C 40D4h |
EPWM5_G0 | 5000 50D4h |
EPWM5_G1 | 5004 50D4h |
EPWM5_G2 | 5008 50D4h |
EPWM5_G3 | 500C 50D4h |
EPWM6_G0 | 5000 60D4h |
EPWM6_G1 | 5004 60D4h |
EPWM6_G2 | 5008 60D4h |
EPWM6_G3 | 500C 60D4h |
EPWM7_G0 | 5000 70D4h |
EPWM7_G1 | 5004 70D4h |
EPWM7_G2 | 5008 70D4h |
EPWM7_G3 | 500C 70D4h |
EPWM8_G0 | 5000 80D4h |
EPWM8_G1 | 5004 80D4h |
EPWM8_G2 | 5008 80D4h |
EPWM8_G3 | 500C 80D4h |
EPWM9_G0 | 5000 90D4h |
EPWM9_G1 | 5004 90D4h |
EPWM9_G2 | 5008 90D4h |
EPWM9_G3 | 500C 90D4h |
EPWM10_G0 | 5000 A0D4h |
EPWM10_G1 | 5004 A0D4h |
EPWM10_G2 | 5008 A0D4h |
EPWM10_G3 | 500C A0D4h |
EPWM11_G0 | 5000 B0D4h |
EPWM11_G1 | 5004 B0D4h |
EPWM11_G2 | 5008 B0D4h |
EPWM11_G3 | 500C B0D4h |
EPWM12_G0 | 5000 C0D4h |
EPWM12_G1 | 5004 C0D4h |
EPWM12_G2 | 5008 C0D4h |
EPWM12_G3 | 500C C0D4h |
EPWM13_G0 | 5000 D0D4h |
EPWM13_G1 | 5004 D0D4h |
EPWM13_G2 | 5008 D0D4h |
EPWM13_G3 | 500C D0D4h |
EPWM14_G0 | 5000 E0D4h |
EPWM14_G1 | 5004 E0D4h |
EPWM14_G2 | 5008 E0D4h |
EPWM14_G3 | 500C E0D4h |
EPWM15_G0 | 5000 F0D4h |
EPWM15_G1 | 5004 F0D4h |
EPWM15_G2 | 5008 F0D4h |
EPWM15_G3 | 500C F0D4h |
EPWM16_G0 | 5001 00D4h |
EPWM16_G1 | 5005 00D4h |
EPWM16_G2 | 5009 00D4h |
EPWM16_G3 | 500D 00D4h |
EPWM17_G0 | 5001 10D4h |
EPWM17_G1 | 5005 10D4h |
EPWM17_G2 | 5009 10D4h |
EPWM17_G3 | 500D 10D4h |
EPWM18_G0 | 5001 20D4h |
EPWM18_G1 | 5005 20D4h |
EPWM18_G2 | 5009 20D4h |
EPWM18_G3 | 500D 20D4h |
EPWM19_G0 | 5001 30D4h |
EPWM19_G1 | 5005 30D4h |
EPWM19_G2 | 5009 30D4h |
EPWM19_G3 | 500D 30D4h |
EPWM20_G0 | 5001 40D4h |
EPWM20_G1 | 5005 40D4h |
EPWM20_G2 | 5009 40D4h |
EPWM20_G3 | 500D 40D4h |
EPWM21_G0 | 5001 50D4h |
EPWM21_G1 | 5005 50D4h |
EPWM21_G2 | 5009 50D4h |
EPWM21_G3 | 500D 50D4h |
EPWM22_G0 | 5001 60D4h |
EPWM22_G1 | 5005 60D4h |
EPWM22_G2 | 5009 60D4h |
EPWM22_G3 | 500D 60D4h |
EPWM23_G0 | 5001 70D4h |
EPWM23_G1 | 5005 70D4h |
EPWM23_G2 | 5009 70D4h |
EPWM23_G3 | 500D 70D4h |
EPWM24_G0 | 5001 80D4h |
EPWM24_G1 | 5005 80D4h |
EPWM24_G2 | 5009 80D4h |
EPWM24_G3 | 500D 80D4h |
EPWM25_G0 | 5001 90D4h |
EPWM25_G1 | 5005 90D4h |
EPWM25_G2 | 5009 90D4h |
EPWM25_G3 | 500D 90D4h |
EPWM26_G0 | 5001 A0D4h |
EPWM26_G1 | 5005 A0D4h |
EPWM26_G2 | 5009 A0D4h |
EPWM26_G3 | 500D A0D4h |
EPWM27_G0 | 5001 B0D4h |
EPWM27_G1 | 5005 B0D4h |
EPWM27_G2 | 5009 B0D4h |
EPWM27_G3 | 500D B0D4h |
EPWM28_G0 | 5001 C0D4h |
EPWM28_G1 | 5005 C0D4h |
EPWM28_G2 | 5009 C0D4h |
EPWM28_G3 | 500D C0D4h |
EPWM29_G0 | 5001 D0D4h |
EPWM29_G1 | 5005 D0D4h |
EPWM29_G2 | 5009 D0D4h |
EPWM29_G3 | 500D D0D4h |
EPWM30_G0 | 5001 E0D4h |
EPWM30_G1 | 5005 E0D4h |
EPWM30_G2 | 5009 E0D4h |
EPWM30_G3 | 500D E0D4h |
EPWM31_G0 | 5001 F0D4h |
EPWM31_G1 | 5005 F0D4h |
EPWM31_G2 | 5009 F0D4h |
EPWM31_G3 | 500D F0D4h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
CMPA | |||||||
R/W | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
CMPA | |||||||
R/W | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CMPAHR | |||||||
R/W | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMPAHR | |||||||
R/W | |||||||
0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:16 | CMPA | R/W | 0h | Compare A Register The value in the active CMPA register is continuously compared to the time-base counter [TBCTR]. When the values are equal, the counter-compare module generates a "time-base counter equal to counter compare A" event. This event is sent to the action-qualifier where it is qualified and converted it into one or more actions. These actions can be applied to either the EPWMxA or the EPWMxB output depending on the configuration of the AQCTLA and AQCTLB registers. The actions that can be defined in the AQCTLA and AQCTLB registers include: - Do nothing the event is ignored. - Clear: Pull the EPWMxA and/or EPWMxB signal low - Set: Pull the EPWMxA and/or EPWMxB signal high - Toggle the EPWMxA and/or EPWMxB signal Shadowing of this register is enabled and disabled by the CMPCTL[SHDWAMODE] bit. By default this register is shadowed. - If CMPCTL[SHDWAMODE] = 0, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the CMPCTL[LOADAMODE] bit field determines which event will load the active register from the shadow register. - Before a write, the CMPCTL[SHDWAFULL] bit can be read to determine if the shadow register is currently full. - If CMPCTL[SHDWAMODE] = 1, then the shadow register is disabled and any write or read will go directly to the active register, that is the register actively controlling the hardware. - In either mode, the active and shadow registers share the same memory map address. |
15:0 | CMPAHR | R/W | 0h | Compare A HRPWM Extension Register The UPPER 8-bits contain the high-resolution portion [most significant 8-bits] of the counter-compare A value. CMPA:CMPAHR can be accessed in a single 32-bit read/write. Shadowing is enabled and disabled by the CMPCTL[SHDWAMODE] bit as described for the CMPA register. The lower 8 bits in this register are ignored |