SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Counter Compare C Register
LINK feature access should always be 16-bit.
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Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 00DEh |
EPWM0_G1 | 5004 00DEh |
EPWM0_G2 | 5008 00DEh |
EPWM0_G3 | 500C 00DEh |
EPWM1_G0 | 5000 10DEh |
EPWM1_G1 | 5004 10DEh |
EPWM1_G2 | 5008 10DEh |
EPWM1_G3 | 500C 10DEh |
EPWM2_G0 | 5000 20DEh |
EPWM2_G1 | 5004 20DEh |
EPWM2_G2 | 5008 20DEh |
EPWM2_G3 | 500C 20DEh |
EPWM3_G0 | 5000 30DEh |
EPWM3_G1 | 5004 30DEh |
EPWM3_G2 | 5008 30DEh |
EPWM3_G3 | 500C 30DEh |
EPWM4_G0 | 5000 40DEh |
EPWM4_G1 | 5004 40DEh |
EPWM4_G2 | 5008 40DEh |
EPWM4_G3 | 500C 40DEh |
EPWM5_G0 | 5000 50DEh |
EPWM5_G1 | 5004 50DEh |
EPWM5_G2 | 5008 50DEh |
EPWM5_G3 | 500C 50DEh |
EPWM6_G0 | 5000 60DEh |
EPWM6_G1 | 5004 60DEh |
EPWM6_G2 | 5008 60DEh |
EPWM6_G3 | 500C 60DEh |
EPWM7_G0 | 5000 70DEh |
EPWM7_G1 | 5004 70DEh |
EPWM7_G2 | 5008 70DEh |
EPWM7_G3 | 500C 70DEh |
EPWM8_G0 | 5000 80DEh |
EPWM8_G1 | 5004 80DEh |
EPWM8_G2 | 5008 80DEh |
EPWM8_G3 | 500C 80DEh |
EPWM9_G0 | 5000 90DEh |
EPWM9_G1 | 5004 90DEh |
EPWM9_G2 | 5008 90DEh |
EPWM9_G3 | 500C 90DEh |
EPWM10_G0 | 5000 A0DEh |
EPWM10_G1 | 5004 A0DEh |
EPWM10_G2 | 5008 A0DEh |
EPWM10_G3 | 500C A0DEh |
EPWM11_G0 | 5000 B0DEh |
EPWM11_G1 | 5004 B0DEh |
EPWM11_G2 | 5008 B0DEh |
EPWM11_G3 | 500C B0DEh |
EPWM12_G0 | 5000 C0DEh |
EPWM12_G1 | 5004 C0DEh |
EPWM12_G2 | 5008 C0DEh |
EPWM12_G3 | 500C C0DEh |
EPWM13_G0 | 5000 D0DEh |
EPWM13_G1 | 5004 D0DEh |
EPWM13_G2 | 5008 D0DEh |
EPWM13_G3 | 500C D0DEh |
EPWM14_G0 | 5000 E0DEh |
EPWM14_G1 | 5004 E0DEh |
EPWM14_G2 | 5008 E0DEh |
EPWM14_G3 | 500C E0DEh |
EPWM15_G0 | 5000 F0DEh |
EPWM15_G1 | 5004 F0DEh |
EPWM15_G2 | 5008 F0DEh |
EPWM15_G3 | 500C F0DEh |
EPWM16_G0 | 5001 00DEh |
EPWM16_G1 | 5005 00DEh |
EPWM16_G2 | 5009 00DEh |
EPWM16_G3 | 500D 00DEh |
EPWM17_G0 | 5001 10DEh |
EPWM17_G1 | 5005 10DEh |
EPWM17_G2 | 5009 10DEh |
EPWM17_G3 | 500D 10DEh |
EPWM18_G0 | 5001 20DEh |
EPWM18_G1 | 5005 20DEh |
EPWM18_G2 | 5009 20DEh |
EPWM18_G3 | 500D 20DEh |
EPWM19_G0 | 5001 30DEh |
EPWM19_G1 | 5005 30DEh |
EPWM19_G2 | 5009 30DEh |
EPWM19_G3 | 500D 30DEh |
EPWM20_G0 | 5001 40DEh |
EPWM20_G1 | 5005 40DEh |
EPWM20_G2 | 5009 40DEh |
EPWM20_G3 | 500D 40DEh |
EPWM21_G0 | 5001 50DEh |
EPWM21_G1 | 5005 50DEh |
EPWM21_G2 | 5009 50DEh |
EPWM21_G3 | 500D 50DEh |
EPWM22_G0 | 5001 60DEh |
EPWM22_G1 | 5005 60DEh |
EPWM22_G2 | 5009 60DEh |
EPWM22_G3 | 500D 60DEh |
EPWM23_G0 | 5001 70DEh |
EPWM23_G1 | 5005 70DEh |
EPWM23_G2 | 5009 70DEh |
EPWM23_G3 | 500D 70DEh |
EPWM24_G0 | 5001 80DEh |
EPWM24_G1 | 5005 80DEh |
EPWM24_G2 | 5009 80DEh |
EPWM24_G3 | 500D 80DEh |
EPWM25_G0 | 5001 90DEh |
EPWM25_G1 | 5005 90DEh |
EPWM25_G2 | 5009 90DEh |
EPWM25_G3 | 500D 90DEh |
EPWM26_G0 | 5001 A0DEh |
EPWM26_G1 | 5005 A0DEh |
EPWM26_G2 | 5009 A0DEh |
EPWM26_G3 | 500D A0DEh |
EPWM27_G0 | 5001 B0DEh |
EPWM27_G1 | 5005 B0DEh |
EPWM27_G2 | 5009 B0DEh |
EPWM27_G3 | 500D B0DEh |
EPWM28_G0 | 5001 C0DEh |
EPWM28_G1 | 5005 C0DEh |
EPWM28_G2 | 5009 C0DEh |
EPWM28_G3 | 500D C0DEh |
EPWM29_G0 | 5001 D0DEh |
EPWM29_G1 | 5005 D0DEh |
EPWM29_G2 | 5009 D0DEh |
EPWM29_G3 | 500D D0DEh |
EPWM30_G0 | 5001 E0DEh |
EPWM30_G1 | 5005 E0DEh |
EPWM30_G2 | 5009 E0DEh |
EPWM30_G3 | 500D E0DEh |
EPWM31_G0 | 5001 F0DEh |
EPWM31_G1 | 5005 F0DEh |
EPWM31_G2 | 5009 F0DEh |
EPWM31_G3 | 500D F0DEh |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
CMPC | |||||||
R/W | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CMPC | |||||||
R/W | |||||||
0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:0 | CMPC | R/W | 0h | Compare C Register The value in the active CMPC register is continuously compared to the time-base counter [TBCTR]. When the values are equal, the counter-compare module generates a "time-base counter equal to counter compare C" event. Shadowing of this register is enabled and disabled by the CMPCTL2[SHDWCMODE] bit. By default this register is shadowed. - If CMPCTL2[SHDWCMODE] = 0, then the shadow is enabled and any write or read will automatically go to the shadow register. In this case, the CMPCTL2[LOADCMODE] bit field determines which event will load the active register from the shadow register: - If CMPCTL2[SHDWCMODE] = 1, then the shadow register is disabled and any write or read will go directly to the active register that is, the register actively controlling the hardware. - In either mode, the active and shadow registers share the same memory map address. |