SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Trip Zone CBC Clear Register.
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Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 0130h |
EPWM0_G1 | 5004 0130h |
EPWM0_G2 | 5008 0130h |
EPWM0_G3 | 500C 0130h |
EPWM1_G0 | 5000 1130h |
EPWM1_G1 | 5004 1130h |
EPWM1_G2 | 5008 1130h |
EPWM1_G3 | 500C 1130h |
EPWM2_G0 | 5000 2130h |
EPWM2_G1 | 5004 2130h |
EPWM2_G2 | 5008 2130h |
EPWM2_G3 | 500C 2130h |
EPWM3_G0 | 5000 3130h |
EPWM3_G1 | 5004 3130h |
EPWM3_G2 | 5008 3130h |
EPWM3_G3 | 500C 3130h |
EPWM4_G0 | 5000 4130h |
EPWM4_G1 | 5004 4130h |
EPWM4_G2 | 5008 4130h |
EPWM4_G3 | 500C 4130h |
EPWM5_G0 | 5000 5130h |
EPWM5_G1 | 5004 5130h |
EPWM5_G2 | 5008 5130h |
EPWM5_G3 | 500C 5130h |
EPWM6_G0 | 5000 6130h |
EPWM6_G1 | 5004 6130h |
EPWM6_G2 | 5008 6130h |
EPWM6_G3 | 500C 6130h |
EPWM7_G0 | 5000 7130h |
EPWM7_G1 | 5004 7130h |
EPWM7_G2 | 5008 7130h |
EPWM7_G3 | 500C 7130h |
EPWM8_G0 | 5000 8130h |
EPWM8_G1 | 5004 8130h |
EPWM8_G2 | 5008 8130h |
EPWM8_G3 | 500C 8130h |
EPWM9_G0 | 5000 9130h |
EPWM9_G1 | 5004 9130h |
EPWM9_G2 | 5008 9130h |
EPWM9_G3 | 500C 9130h |
EPWM10_G0 | 5000 A130h |
EPWM10_G1 | 5004 A130h |
EPWM10_G2 | 5008 A130h |
EPWM10_G3 | 500C A130h |
EPWM11_G0 | 5000 B130h |
EPWM11_G1 | 5004 B130h |
EPWM11_G2 | 5008 B130h |
EPWM11_G3 | 500C B130h |
EPWM12_G0 | 5000 C130h |
EPWM12_G1 | 5004 C130h |
EPWM12_G2 | 5008 C130h |
EPWM12_G3 | 500C C130h |
EPWM13_G0 | 5000 D130h |
EPWM13_G1 | 5004 D130h |
EPWM13_G2 | 5008 D130h |
EPWM13_G3 | 500C D130h |
EPWM14_G0 | 5000 E130h |
EPWM14_G1 | 5004 E130h |
EPWM14_G2 | 5008 E130h |
EPWM14_G3 | 500C E130h |
EPWM15_G0 | 5000 F130h |
EPWM15_G1 | 5004 F130h |
EPWM15_G2 | 5008 F130h |
EPWM15_G3 | 500C F130h |
EPWM16_G0 | 5001 0130h |
EPWM16_G1 | 5005 0130h |
EPWM16_G2 | 5009 0130h |
EPWM16_G3 | 500D 0130h |
EPWM17_G0 | 5001 1130h |
EPWM17_G1 | 5005 1130h |
EPWM17_G2 | 5009 1130h |
EPWM17_G3 | 500D 1130h |
EPWM18_G0 | 5001 2130h |
EPWM18_G1 | 5005 2130h |
EPWM18_G2 | 5009 2130h |
EPWM18_G3 | 500D 2130h |
EPWM19_G0 | 5001 3130h |
EPWM19_G1 | 5005 3130h |
EPWM19_G2 | 5009 3130h |
EPWM19_G3 | 500D 3130h |
EPWM20_G0 | 5001 4130h |
EPWM20_G1 | 5005 4130h |
EPWM20_G2 | 5009 4130h |
EPWM20_G3 | 500D 4130h |
EPWM21_G0 | 5001 5130h |
EPWM21_G1 | 5005 5130h |
EPWM21_G2 | 5009 5130h |
EPWM21_G3 | 500D 5130h |
EPWM22_G0 | 5001 6130h |
EPWM22_G1 | 5005 6130h |
EPWM22_G2 | 5009 6130h |
EPWM22_G3 | 500D 6130h |
EPWM23_G0 | 5001 7130h |
EPWM23_G1 | 5005 7130h |
EPWM23_G2 | 5009 7130h |
EPWM23_G3 | 500D 7130h |
EPWM24_G0 | 5001 8130h |
EPWM24_G1 | 5005 8130h |
EPWM24_G2 | 5009 8130h |
EPWM24_G3 | 500D 8130h |
EPWM25_G0 | 5001 9130h |
EPWM25_G1 | 5005 9130h |
EPWM25_G2 | 5009 9130h |
EPWM25_G3 | 500D 9130h |
EPWM26_G0 | 5001 A130h |
EPWM26_G1 | 5005 A130h |
EPWM26_G2 | 5009 A130h |
EPWM26_G3 | 500D A130h |
EPWM27_G0 | 5001 B130h |
EPWM27_G1 | 5005 B130h |
EPWM27_G2 | 5009 B130h |
EPWM27_G3 | 500D B130h |
EPWM28_G0 | 5001 C130h |
EPWM28_G1 | 5005 C130h |
EPWM28_G2 | 5009 C130h |
EPWM28_G3 | 500D C130h |
EPWM29_G0 | 5001 D130h |
EPWM29_G1 | 5005 D130h |
EPWM29_G2 | 5009 D130h |
EPWM29_G3 | 500D D130h |
EPWM30_G0 | 5001 E130h |
EPWM30_G1 | 5005 E130h |
EPWM30_G2 | 5009 E130h |
EPWM30_G3 | 500D E130h |
EPWM31_G0 | 5001 F130h |
EPWM31_G1 | 5005 F130h |
EPWM31_G2 | 5009 F130h |
EPWM31_G3 | 500D F130h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED_1 | CAPEVT | ||||||
R | R/W1TS | ||||||
0h | 0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DCBEVT2 | DCAEVT2 | CBC6 | CBC5 | CBC4 | CBC3 | CBC2 | CBC1 |
R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:9 | RESERVED_1 | R | 0h | Reserved |
8 | CAPEVT | R/W1TS | 0h | Clear Flag for CAPEVT selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CAPEVT] bit. |
7 | DCBEVT2 | R/W1TS | 0h | Clear Flag for Digital Compare Output B Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCBEVT2] bit. |
6 | DCAEVT2 | R/W1TS | 0h | Clear Flag for Digital Compare Output A Event 2 selected for CBC 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[DCAEVT2] bit. |
5 | CBC6 | R/W1TS | 0h | Clear Flag for Cycle-By-Cycle [CBC6] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC6] bit. |
4 | CBC5 | R/W1TS | 0h | Clear Flag for Cycle-By-Cycle [CBC5] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC5] bit. |
3 | CBC4 | R/W1TS | 0h | Clear Flag for Cycle-By-Cycle [CBC4] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC4] bit. |
2 | CBC3 | R/W1TS | 0h | Clear Flag for Cycle-By-Cycle [CBC3] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC3] bit. |
1 | CBC2 | R/W1TS | 0h | Clear Flag for Cycle-By-Cycle [CBC2] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC2] bit. |
0 | CBC1 | R/W1TS | 0h | Clear Flag for Cycle-By-Cycle [CBC1] Trip Latch 0:Writing a 0 has no effect. 1:Writing a 1 will clear the TZCBCFLG[CBC1] bit. |