SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Trip Zone Force Register.
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Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 0136h |
EPWM0_G1 | 5004 0136h |
EPWM0_G2 | 5008 0136h |
EPWM0_G3 | 500C 0136h |
EPWM1_G0 | 5000 1136h |
EPWM1_G1 | 5004 1136h |
EPWM1_G2 | 5008 1136h |
EPWM1_G3 | 500C 1136h |
EPWM2_G0 | 5000 2136h |
EPWM2_G1 | 5004 2136h |
EPWM2_G2 | 5008 2136h |
EPWM2_G3 | 500C 2136h |
EPWM3_G0 | 5000 3136h |
EPWM3_G1 | 5004 3136h |
EPWM3_G2 | 5008 3136h |
EPWM3_G3 | 500C 3136h |
EPWM4_G0 | 5000 4136h |
EPWM4_G1 | 5004 4136h |
EPWM4_G2 | 5008 4136h |
EPWM4_G3 | 500C 4136h |
EPWM5_G0 | 5000 5136h |
EPWM5_G1 | 5004 5136h |
EPWM5_G2 | 5008 5136h |
EPWM5_G3 | 500C 5136h |
EPWM6_G0 | 5000 6136h |
EPWM6_G1 | 5004 6136h |
EPWM6_G2 | 5008 6136h |
EPWM6_G3 | 500C 6136h |
EPWM7_G0 | 5000 7136h |
EPWM7_G1 | 5004 7136h |
EPWM7_G2 | 5008 7136h |
EPWM7_G3 | 500C 7136h |
EPWM8_G0 | 5000 8136h |
EPWM8_G1 | 5004 8136h |
EPWM8_G2 | 5008 8136h |
EPWM8_G3 | 500C 8136h |
EPWM9_G0 | 5000 9136h |
EPWM9_G1 | 5004 9136h |
EPWM9_G2 | 5008 9136h |
EPWM9_G3 | 500C 9136h |
EPWM10_G0 | 5000 A136h |
EPWM10_G1 | 5004 A136h |
EPWM10_G2 | 5008 A136h |
EPWM10_G3 | 500C A136h |
EPWM11_G0 | 5000 B136h |
EPWM11_G1 | 5004 B136h |
EPWM11_G2 | 5008 B136h |
EPWM11_G3 | 500C B136h |
EPWM12_G0 | 5000 C136h |
EPWM12_G1 | 5004 C136h |
EPWM12_G2 | 5008 C136h |
EPWM12_G3 | 500C C136h |
EPWM13_G0 | 5000 D136h |
EPWM13_G1 | 5004 D136h |
EPWM13_G2 | 5008 D136h |
EPWM13_G3 | 500C D136h |
EPWM14_G0 | 5000 E136h |
EPWM14_G1 | 5004 E136h |
EPWM14_G2 | 5008 E136h |
EPWM14_G3 | 500C E136h |
EPWM15_G0 | 5000 F136h |
EPWM15_G1 | 5004 F136h |
EPWM15_G2 | 5008 F136h |
EPWM15_G3 | 500C F136h |
EPWM16_G0 | 5001 0136h |
EPWM16_G1 | 5005 0136h |
EPWM16_G2 | 5009 0136h |
EPWM16_G3 | 500D 0136h |
EPWM17_G0 | 5001 1136h |
EPWM17_G1 | 5005 1136h |
EPWM17_G2 | 5009 1136h |
EPWM17_G3 | 500D 1136h |
EPWM18_G0 | 5001 2136h |
EPWM18_G1 | 5005 2136h |
EPWM18_G2 | 5009 2136h |
EPWM18_G3 | 500D 2136h |
EPWM19_G0 | 5001 3136h |
EPWM19_G1 | 5005 3136h |
EPWM19_G2 | 5009 3136h |
EPWM19_G3 | 500D 3136h |
EPWM20_G0 | 5001 4136h |
EPWM20_G1 | 5005 4136h |
EPWM20_G2 | 5009 4136h |
EPWM20_G3 | 500D 4136h |
EPWM21_G0 | 5001 5136h |
EPWM21_G1 | 5005 5136h |
EPWM21_G2 | 5009 5136h |
EPWM21_G3 | 500D 5136h |
EPWM22_G0 | 5001 6136h |
EPWM22_G1 | 5005 6136h |
EPWM22_G2 | 5009 6136h |
EPWM22_G3 | 500D 6136h |
EPWM23_G0 | 5001 7136h |
EPWM23_G1 | 5005 7136h |
EPWM23_G2 | 5009 7136h |
EPWM23_G3 | 500D 7136h |
EPWM24_G0 | 5001 8136h |
EPWM24_G1 | 5005 8136h |
EPWM24_G2 | 5009 8136h |
EPWM24_G3 | 500D 8136h |
EPWM25_G0 | 5001 9136h |
EPWM25_G1 | 5005 9136h |
EPWM25_G2 | 5009 9136h |
EPWM25_G3 | 500D 9136h |
EPWM26_G0 | 5001 A136h |
EPWM26_G1 | 5005 A136h |
EPWM26_G2 | 5009 A136h |
EPWM26_G3 | 500D A136h |
EPWM27_G0 | 5001 B136h |
EPWM27_G1 | 5005 B136h |
EPWM27_G2 | 5009 B136h |
EPWM27_G3 | 500D B136h |
EPWM28_G0 | 5001 C136h |
EPWM28_G1 | 5005 C136h |
EPWM28_G2 | 5009 C136h |
EPWM28_G3 | 500D C136h |
EPWM29_G0 | 5001 D136h |
EPWM29_G1 | 5005 D136h |
EPWM29_G2 | 5009 D136h |
EPWM29_G3 | 500D D136h |
EPWM30_G0 | 5001 E136h |
EPWM30_G1 | 5005 E136h |
EPWM30_G2 | 5009 E136h |
EPWM30_G3 | 500D E136h |
EPWM31_G0 | 5001 F136h |
EPWM31_G1 | 5005 F136h |
EPWM31_G2 | 5009 F136h |
EPWM31_G3 | 500D F136h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED_2 | |||||||
R | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
CAPEVT | DCBEVT2 | DCBEVT1 | DCAEVT2 | DCAEVT1 | OST | CBC | RESERVED_1 |
R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R/W1TS | R |
0h | 0h | 0h | 0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | RESERVED_2 | R | 0h | Reserved |
7 | CAPEVT | R/W1TS | 0h | Force Flag for Capture Event Output 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the CAPEVT event trip condition and sets the TZFLG[CAPEVT] bit. |
6 | DCBEVT2 | R/W1TS | 0h | Force Flag for Digital Compare Output B Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT2 event trip condition and sets the TZFLG[DCBEVT2] bit. |
5 | DCBEVT1 | R/W1TS | 0h | Force Flag for Digital Compare Output B Event 1 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCBEVT1 event trip condition and sets the TZFLG[DCBEVT1] bit. |
4 | DCAEVT2 | R/W1TS | 0h | Force Flag for Digital Compare Output A Event 2 0:Writing 0 has no effect. This bit always reads back 0. 1:Writing 1 forces the DCAEVT2 event trip condition and sets the TZFLG[DCAEVT2] bit. |
3 | DCAEVT1 | R/W1TS | 0h | Force Flag for Digital Compare Output A Event 1 0:Writing 0 has no effect. This bit always reads back 0 1:Writing 1 forces the DCAEVT1 event trip condition and sets the TZFLG[DCAEVT1] bit. |
2 | OST | R/W1TS | 0h | Force a One-Shot Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a one-shot trip event and sets the TZFLG[OST] bit. |
1 | CBC | R/W1TS | 0h | Force a Cycle-by-Cycle Trip Event via Software 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a cycle-by-cycle trip event and sets the TZFLG[CBC] bit. |
0 | RESERVED_1 | R | 0h | Reserved |