SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Event Trigger Force Register.
Return to Summary Table
Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 0158h |
EPWM0_G1 | 5004 0158h |
EPWM0_G2 | 5008 0158h |
EPWM0_G3 | 500C 0158h |
EPWM1_G0 | 5000 1158h |
EPWM1_G1 | 5004 1158h |
EPWM1_G2 | 5008 1158h |
EPWM1_G3 | 500C 1158h |
EPWM2_G0 | 5000 2158h |
EPWM2_G1 | 5004 2158h |
EPWM2_G2 | 5008 2158h |
EPWM2_G3 | 500C 2158h |
EPWM3_G0 | 5000 3158h |
EPWM3_G1 | 5004 3158h |
EPWM3_G2 | 5008 3158h |
EPWM3_G3 | 500C 3158h |
EPWM4_G0 | 5000 4158h |
EPWM4_G1 | 5004 4158h |
EPWM4_G2 | 5008 4158h |
EPWM4_G3 | 500C 4158h |
EPWM5_G0 | 5000 5158h |
EPWM5_G1 | 5004 5158h |
EPWM5_G2 | 5008 5158h |
EPWM5_G3 | 500C 5158h |
EPWM6_G0 | 5000 6158h |
EPWM6_G1 | 5004 6158h |
EPWM6_G2 | 5008 6158h |
EPWM6_G3 | 500C 6158h |
EPWM7_G0 | 5000 7158h |
EPWM7_G1 | 5004 7158h |
EPWM7_G2 | 5008 7158h |
EPWM7_G3 | 500C 7158h |
EPWM8_G0 | 5000 8158h |
EPWM8_G1 | 5004 8158h |
EPWM8_G2 | 5008 8158h |
EPWM8_G3 | 500C 8158h |
EPWM9_G0 | 5000 9158h |
EPWM9_G1 | 5004 9158h |
EPWM9_G2 | 5008 9158h |
EPWM9_G3 | 500C 9158h |
EPWM10_G0 | 5000 A158h |
EPWM10_G1 | 5004 A158h |
EPWM10_G2 | 5008 A158h |
EPWM10_G3 | 500C A158h |
EPWM11_G0 | 5000 B158h |
EPWM11_G1 | 5004 B158h |
EPWM11_G2 | 5008 B158h |
EPWM11_G3 | 500C B158h |
EPWM12_G0 | 5000 C158h |
EPWM12_G1 | 5004 C158h |
EPWM12_G2 | 5008 C158h |
EPWM12_G3 | 500C C158h |
EPWM13_G0 | 5000 D158h |
EPWM13_G1 | 5004 D158h |
EPWM13_G2 | 5008 D158h |
EPWM13_G3 | 500C D158h |
EPWM14_G0 | 5000 E158h |
EPWM14_G1 | 5004 E158h |
EPWM14_G2 | 5008 E158h |
EPWM14_G3 | 500C E158h |
EPWM15_G0 | 5000 F158h |
EPWM15_G1 | 5004 F158h |
EPWM15_G2 | 5008 F158h |
EPWM15_G3 | 500C F158h |
EPWM16_G0 | 5001 0158h |
EPWM16_G1 | 5005 0158h |
EPWM16_G2 | 5009 0158h |
EPWM16_G3 | 500D 0158h |
EPWM17_G0 | 5001 1158h |
EPWM17_G1 | 5005 1158h |
EPWM17_G2 | 5009 1158h |
EPWM17_G3 | 500D 1158h |
EPWM18_G0 | 5001 2158h |
EPWM18_G1 | 5005 2158h |
EPWM18_G2 | 5009 2158h |
EPWM18_G3 | 500D 2158h |
EPWM19_G0 | 5001 3158h |
EPWM19_G1 | 5005 3158h |
EPWM19_G2 | 5009 3158h |
EPWM19_G3 | 500D 3158h |
EPWM20_G0 | 5001 4158h |
EPWM20_G1 | 5005 4158h |
EPWM20_G2 | 5009 4158h |
EPWM20_G3 | 500D 4158h |
EPWM21_G0 | 5001 5158h |
EPWM21_G1 | 5005 5158h |
EPWM21_G2 | 5009 5158h |
EPWM21_G3 | 500D 5158h |
EPWM22_G0 | 5001 6158h |
EPWM22_G1 | 5005 6158h |
EPWM22_G2 | 5009 6158h |
EPWM22_G3 | 500D 6158h |
EPWM23_G0 | 5001 7158h |
EPWM23_G1 | 5005 7158h |
EPWM23_G2 | 5009 7158h |
EPWM23_G3 | 500D 7158h |
EPWM24_G0 | 5001 8158h |
EPWM24_G1 | 5005 8158h |
EPWM24_G2 | 5009 8158h |
EPWM24_G3 | 500D 8158h |
EPWM25_G0 | 5001 9158h |
EPWM25_G1 | 5005 9158h |
EPWM25_G2 | 5009 9158h |
EPWM25_G3 | 500D 9158h |
EPWM26_G0 | 5001 A158h |
EPWM26_G1 | 5005 A158h |
EPWM26_G2 | 5009 A158h |
EPWM26_G3 | 500D A158h |
EPWM27_G0 | 5001 B158h |
EPWM27_G1 | 5005 B158h |
EPWM27_G2 | 5009 B158h |
EPWM27_G3 | 500D B158h |
EPWM28_G0 | 5001 C158h |
EPWM28_G1 | 5005 C158h |
EPWM28_G2 | 5009 C158h |
EPWM28_G3 | 500D C158h |
EPWM29_G0 | 5001 D158h |
EPWM29_G1 | 5005 D158h |
EPWM29_G2 | 5009 D158h |
EPWM29_G3 | 500D D158h |
EPWM30_G0 | 5001 E158h |
EPWM30_G1 | 5005 E158h |
EPWM30_G2 | 5009 E158h |
EPWM30_G3 | 500D E158h |
EPWM31_G0 | 5001 F158h |
EPWM31_G1 | 5005 F158h |
EPWM31_G2 | 5009 F158h |
EPWM31_G3 | 500D F158h |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED_2 | |||||||
R | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_2 | SOCB | SOCA | RESERVED_1 | INT | |||
R | R/W1TS | R/W1TS | R | R/W1TS | |||
0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:4 | RESERVED_2 | R | 0h | Reserved |
3 | SOCB | R/W1TS | 0h | SOCB Force Bit The SOCB pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCB] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCB and set the SOCBFLG bit. This bit is used for test purposes. |
2 | SOCA | R/W1TS | 0h | SOCA Force Bit The SOCA pulse will only be generated if the event is enabled in the ETSEL register. The ETFLG[SOCA] flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates a pulse on EPWMxSOCA and set the SOCAFLG bit. This bit is used for test purposes. |
1 | RESERVED_1 | R | 0h | Reserved |
0 | INT | R/W1TS | 0h | INT Force Bit The interrupt will only be generated if the event is enabled in the ETSEL register. The INT flag bit will be set regardless. 0:Writing 0 to this bit will be ignored. Always reads back a 0. 1:Generates an interrupt on EPWMxINT and set the INT flag bit. This bit is used for test purposes. |