SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Digital Compare Filter Control Register.
Return to Summary Table
Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 018Eh |
EPWM0_G1 | 5004 018Eh |
EPWM0_G2 | 5008 018Eh |
EPWM0_G3 | 500C 018Eh |
EPWM1_G0 | 5000 118Eh |
EPWM1_G1 | 5004 118Eh |
EPWM1_G2 | 5008 118Eh |
EPWM1_G3 | 500C 118Eh |
EPWM2_G0 | 5000 218Eh |
EPWM2_G1 | 5004 218Eh |
EPWM2_G2 | 5008 218Eh |
EPWM2_G3 | 500C 218Eh |
EPWM3_G0 | 5000 318Eh |
EPWM3_G1 | 5004 318Eh |
EPWM3_G2 | 5008 318Eh |
EPWM3_G3 | 500C 318Eh |
EPWM4_G0 | 5000 418Eh |
EPWM4_G1 | 5004 418Eh |
EPWM4_G2 | 5008 418Eh |
EPWM4_G3 | 500C 418Eh |
EPWM5_G0 | 5000 518Eh |
EPWM5_G1 | 5004 518Eh |
EPWM5_G2 | 5008 518Eh |
EPWM5_G3 | 500C 518Eh |
EPWM6_G0 | 5000 618Eh |
EPWM6_G1 | 5004 618Eh |
EPWM6_G2 | 5008 618Eh |
EPWM6_G3 | 500C 618Eh |
EPWM7_G0 | 5000 718Eh |
EPWM7_G1 | 5004 718Eh |
EPWM7_G2 | 5008 718Eh |
EPWM7_G3 | 500C 718Eh |
EPWM8_G0 | 5000 818Eh |
EPWM8_G1 | 5004 818Eh |
EPWM8_G2 | 5008 818Eh |
EPWM8_G3 | 500C 818Eh |
EPWM9_G0 | 5000 918Eh |
EPWM9_G1 | 5004 918Eh |
EPWM9_G2 | 5008 918Eh |
EPWM9_G3 | 500C 918Eh |
EPWM10_G0 | 5000 A18Eh |
EPWM10_G1 | 5004 A18Eh |
EPWM10_G2 | 5008 A18Eh |
EPWM10_G3 | 500C A18Eh |
EPWM11_G0 | 5000 B18Eh |
EPWM11_G1 | 5004 B18Eh |
EPWM11_G2 | 5008 B18Eh |
EPWM11_G3 | 500C B18Eh |
EPWM12_G0 | 5000 C18Eh |
EPWM12_G1 | 5004 C18Eh |
EPWM12_G2 | 5008 C18Eh |
EPWM12_G3 | 500C C18Eh |
EPWM13_G0 | 5000 D18Eh |
EPWM13_G1 | 5004 D18Eh |
EPWM13_G2 | 5008 D18Eh |
EPWM13_G3 | 500C D18Eh |
EPWM14_G0 | 5000 E18Eh |
EPWM14_G1 | 5004 E18Eh |
EPWM14_G2 | 5008 E18Eh |
EPWM14_G3 | 500C E18Eh |
EPWM15_G0 | 5000 F18Eh |
EPWM15_G1 | 5004 F18Eh |
EPWM15_G2 | 5008 F18Eh |
EPWM15_G3 | 500C F18Eh |
EPWM16_G0 | 5001 018Eh |
EPWM16_G1 | 5005 018Eh |
EPWM16_G2 | 5009 018Eh |
EPWM16_G3 | 500D 018Eh |
EPWM17_G0 | 5001 118Eh |
EPWM17_G1 | 5005 118Eh |
EPWM17_G2 | 5009 118Eh |
EPWM17_G3 | 500D 118Eh |
EPWM18_G0 | 5001 218Eh |
EPWM18_G1 | 5005 218Eh |
EPWM18_G2 | 5009 218Eh |
EPWM18_G3 | 500D 218Eh |
EPWM19_G0 | 5001 318Eh |
EPWM19_G1 | 5005 318Eh |
EPWM19_G2 | 5009 318Eh |
EPWM19_G3 | 500D 318Eh |
EPWM20_G0 | 5001 418Eh |
EPWM20_G1 | 5005 418Eh |
EPWM20_G2 | 5009 418Eh |
EPWM20_G3 | 500D 418Eh |
EPWM21_G0 | 5001 518Eh |
EPWM21_G1 | 5005 518Eh |
EPWM21_G2 | 5009 518Eh |
EPWM21_G3 | 500D 518Eh |
EPWM22_G0 | 5001 618Eh |
EPWM22_G1 | 5005 618Eh |
EPWM22_G2 | 5009 618Eh |
EPWM22_G3 | 500D 618Eh |
EPWM23_G0 | 5001 718Eh |
EPWM23_G1 | 5005 718Eh |
EPWM23_G2 | 5009 718Eh |
EPWM23_G3 | 500D 718Eh |
EPWM24_G0 | 5001 818Eh |
EPWM24_G1 | 5005 818Eh |
EPWM24_G2 | 5009 818Eh |
EPWM24_G3 | 500D 818Eh |
EPWM25_G0 | 5001 918Eh |
EPWM25_G1 | 5005 918Eh |
EPWM25_G2 | 5009 918Eh |
EPWM25_G3 | 500D 918Eh |
EPWM26_G0 | 5001 A18Eh |
EPWM26_G1 | 5005 A18Eh |
EPWM26_G2 | 5009 A18Eh |
EPWM26_G3 | 500D A18Eh |
EPWM27_G0 | 5001 B18Eh |
EPWM27_G1 | 5005 B18Eh |
EPWM27_G2 | 5009 B18Eh |
EPWM27_G3 | 500D B18Eh |
EPWM28_G0 | 5001 C18Eh |
EPWM28_G1 | 5005 C18Eh |
EPWM28_G2 | 5009 C18Eh |
EPWM28_G3 | 500D C18Eh |
EPWM29_G0 | 5001 D18Eh |
EPWM29_G1 | 5005 D18Eh |
EPWM29_G2 | 5009 D18Eh |
EPWM29_G3 | 500D D18Eh |
EPWM30_G0 | 5001 E18Eh |
EPWM30_G1 | 5005 E18Eh |
EPWM30_G2 | 5009 E18Eh |
EPWM30_G3 | 500D E18Eh |
EPWM31_G0 | 5001 F18Eh |
EPWM31_G1 | 5005 F18Eh |
EPWM31_G2 | 5009 F18Eh |
EPWM31_G3 | 500D F18Eh |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
EDGESTATUS | EDGECOUNT | EDGEMODE | |||||
R | R/W | R/W | |||||
0h | 0h | 0h | |||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | EDGEFILTSEL | PULSESEL | BLANKINV | BLANKE | SRCSEL | ||
R | R/W | R/W | R/W | R/W | R/W | ||
0h | 0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:13 | EDGESTATUS | R | 0h | Edge Status: These bits reflect the total number of edges currently captured. When the value matches the EDGECOUNT, the status bits are set to zero. and a TBCLK wide pulse is generated which can then be output on the DCEVTFILT signal. The edge counter can be reset by Writing 000 to the EDGECOUNT value: |
12:10 | EDGECOUNT | R/W | 0h | Edge Count: These bits select how many edges to count before generating a TBCLK wide pulse on the DCEVTFILT signal: 000:no edges, reset current EDGESTATUS bits to 3'b000 001:1 edge 010:2 edges 011:3 edges 100:4 edges 101:5 edges 110:6 edges 111:7 edges |
9:8 | EDGEMODE | R/W | 0h | Edge Mode Select: 00:Low To High Edge 01:High To Low Edge 10:Both Edges 11:Reserved |
7 | RESERVED_1 | R | 0h | Reserved |
6 | EDGEFILTSEL | R/W | 0h | Edge Filter Select: 0:Edge Filter Not Selected 1:Edge Filter Selected |
5:4 | PULSESEL | R/W | 0h | Pulse Select For Blanking & Capture Alignment 00:Time-base counter equal to period [TBCTR = TBPRD] 01:Time-base counter equal to zero [TBCTR = 0x00] 10:Time-base counter equal to zero [TBCTR = 0x00] or period [TBCTR = TBPRD] 11:Blank Pulse Mix |
3 | BLANKINV | R/W | 0h | Blanking Window Inversion 0:Blanking window not inverted 1:Blanking window inverted |
2 | BLANKE | R/W | 0h | Blanking Window Enable/Disable 0:Blanking window is disabled 1:Blanking window is enabled |
1:0 | SRCSEL | R/W | 0h | Filter Block Signal Source Select 00:Source Is DCAEVT1 Signal 01:Source Is DCAEVT2 Signal 10:Source Is DCBEVT1 Signal 11:Source Is DCBEVT2 Signal |