SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Event Capture Control Register.
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Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 01ACh |
EPWM0_G1 | 5004 01ACh |
EPWM0_G2 | 5008 01ACh |
EPWM0_G3 | 500C 01ACh |
EPWM1_G0 | 5000 11ACh |
EPWM1_G1 | 5004 11ACh |
EPWM1_G2 | 5008 11ACh |
EPWM1_G3 | 500C 11ACh |
EPWM2_G0 | 5000 21ACh |
EPWM2_G1 | 5004 21ACh |
EPWM2_G2 | 5008 21ACh |
EPWM2_G3 | 500C 21ACh |
EPWM3_G0 | 5000 31ACh |
EPWM3_G1 | 5004 31ACh |
EPWM3_G2 | 5008 31ACh |
EPWM3_G3 | 500C 31ACh |
EPWM4_G0 | 5000 41ACh |
EPWM4_G1 | 5004 41ACh |
EPWM4_G2 | 5008 41ACh |
EPWM4_G3 | 500C 41ACh |
EPWM5_G0 | 5000 51ACh |
EPWM5_G1 | 5004 51ACh |
EPWM5_G2 | 5008 51ACh |
EPWM5_G3 | 500C 51ACh |
EPWM6_G0 | 5000 61ACh |
EPWM6_G1 | 5004 61ACh |
EPWM6_G2 | 5008 61ACh |
EPWM6_G3 | 500C 61ACh |
EPWM7_G0 | 5000 71ACh |
EPWM7_G1 | 5004 71ACh |
EPWM7_G2 | 5008 71ACh |
EPWM7_G3 | 500C 71ACh |
EPWM8_G0 | 5000 81ACh |
EPWM8_G1 | 5004 81ACh |
EPWM8_G2 | 5008 81ACh |
EPWM8_G3 | 500C 81ACh |
EPWM9_G0 | 5000 91ACh |
EPWM9_G1 | 5004 91ACh |
EPWM9_G2 | 5008 91ACh |
EPWM9_G3 | 500C 91ACh |
EPWM10_G0 | 5000 A1ACh |
EPWM10_G1 | 5004 A1ACh |
EPWM10_G2 | 5008 A1ACh |
EPWM10_G3 | 500C A1ACh |
EPWM11_G0 | 5000 B1ACh |
EPWM11_G1 | 5004 B1ACh |
EPWM11_G2 | 5008 B1ACh |
EPWM11_G3 | 500C B1ACh |
EPWM12_G0 | 5000 C1ACh |
EPWM12_G1 | 5004 C1ACh |
EPWM12_G2 | 5008 C1ACh |
EPWM12_G3 | 500C C1ACh |
EPWM13_G0 | 5000 D1ACh |
EPWM13_G1 | 5004 D1ACh |
EPWM13_G2 | 5008 D1ACh |
EPWM13_G3 | 500C D1ACh |
EPWM14_G0 | 5000 E1ACh |
EPWM14_G1 | 5004 E1ACh |
EPWM14_G2 | 5008 E1ACh |
EPWM14_G3 | 500C E1ACh |
EPWM15_G0 | 5000 F1ACh |
EPWM15_G1 | 5004 F1ACh |
EPWM15_G2 | 5008 F1ACh |
EPWM15_G3 | 500C F1ACh |
EPWM16_G0 | 5001 01ACh |
EPWM16_G1 | 5005 01ACh |
EPWM16_G2 | 5009 01ACh |
EPWM16_G3 | 500D 01ACh |
EPWM17_G0 | 5001 11ACh |
EPWM17_G1 | 5005 11ACh |
EPWM17_G2 | 5009 11ACh |
EPWM17_G3 | 500D 11ACh |
EPWM18_G0 | 5001 21ACh |
EPWM18_G1 | 5005 21ACh |
EPWM18_G2 | 5009 21ACh |
EPWM18_G3 | 500D 21ACh |
EPWM19_G0 | 5001 31ACh |
EPWM19_G1 | 5005 31ACh |
EPWM19_G2 | 5009 31ACh |
EPWM19_G3 | 500D 31ACh |
EPWM20_G0 | 5001 41ACh |
EPWM20_G1 | 5005 41ACh |
EPWM20_G2 | 5009 41ACh |
EPWM20_G3 | 500D 41ACh |
EPWM21_G0 | 5001 51ACh |
EPWM21_G1 | 5005 51ACh |
EPWM21_G2 | 5009 51ACh |
EPWM21_G3 | 500D 51ACh |
EPWM22_G0 | 5001 61ACh |
EPWM22_G1 | 5005 61ACh |
EPWM22_G2 | 5009 61ACh |
EPWM22_G3 | 500D 61ACh |
EPWM23_G0 | 5001 71ACh |
EPWM23_G1 | 5005 71ACh |
EPWM23_G2 | 5009 71ACh |
EPWM23_G3 | 500D 71ACh |
EPWM24_G0 | 5001 81ACh |
EPWM24_G1 | 5005 81ACh |
EPWM24_G2 | 5009 81ACh |
EPWM24_G3 | 500D 81ACh |
EPWM25_G0 | 5001 91ACh |
EPWM25_G1 | 5005 91ACh |
EPWM25_G2 | 5009 91ACh |
EPWM25_G3 | 500D 91ACh |
EPWM26_G0 | 5001 A1ACh |
EPWM26_G1 | 5005 A1ACh |
EPWM26_G2 | 5009 A1ACh |
EPWM26_G3 | 500D A1ACh |
EPWM27_G0 | 5001 B1ACh |
EPWM27_G1 | 5005 B1ACh |
EPWM27_G2 | 5009 B1ACh |
EPWM27_G3 | 500D B1ACh |
EPWM28_G0 | 5001 C1ACh |
EPWM28_G1 | 5005 C1ACh |
EPWM28_G2 | 5009 C1ACh |
EPWM28_G3 | 500D C1ACh |
EPWM29_G0 | 5001 D1ACh |
EPWM29_G1 | 5005 D1ACh |
EPWM29_G2 | 5009 D1ACh |
EPWM29_G3 | 500D D1ACh |
EPWM30_G0 | 5001 E1ACh |
EPWM30_G1 | 5005 E1ACh |
EPWM30_G2 | 5009 E1ACh |
EPWM30_G3 | 500D E1ACh |
EPWM31_G0 | 5001 F1ACh |
EPWM31_G1 | 5005 F1ACh |
EPWM31_G2 | 5009 F1ACh |
EPWM31_G3 | 500D F1ACh |
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED_2 | FRCLOAD | ||||||
R | R/W1TS | ||||||
0h | 0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
RESERVED_1 | PULSECTL | CAPINPOL | CAPGATEPOL | SRCSEL | |||
R | R/W | R/W | R/W | R/W | |||
0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:9 | RESERVED_2 | R | 0h | Reserved |
8 | FRCLOAD | R/W1TS | 0h | 0:Writing of 0 is ignored. Always reads back a 0. 1:Forces a LOAD to occur on the DCC0P - an equivalent LOAD.active pulse |
7:5 | RESERVED_1 | R | 0h | Reserved |
4 | PULSECTL | R/W | 0h | Capture Input Polarity Select Mux: 0:Pulse selection determined by PULSESEL bits [common pulse selection for Blanking and Capture logic] 1:Pulse selection determined by CAPMIXSEL register [independent pulse selection for Blaning and Capture logic] |
3 | CAPINPOL | R/W | 0h | Capture Input Polarity Select Mux: 0:CAPIN.sync not inverted 1:CAPIN.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured |
2:1 | CAPGATEPOL | R/W | 0h | Capture Gate Input Polarity Select Mux: 00:Set to 1 - Gate is always ON 01:Set to 0 - Gate is always OFF 10:CAPGATE.sync 11:CAPGATE.sync Inverted Default state assumption for these inputs can be active high. If the user is providing active low signal then invert option can be configured |
0 | SRCSEL | R/W | 0h | Capture Logic Input Select Mux: 0:DCEVTFILT [Sync] - same as Type-4 1:CAPIN.sync |