SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Minimum dead band configuration register.
Return to Summary Table
Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 0C00h |
EPWM0_G1 | 5004 0C00h |
EPWM0_G2 | 5008 0C00h |
EPWM0_G3 | 500C 0C00h |
EPWM1_G0 | 5000 1C00h |
EPWM1_G1 | 5004 1C00h |
EPWM1_G2 | 5008 1C00h |
EPWM1_G3 | 500C 1C00h |
EPWM2_G0 | 5000 2C00h |
EPWM2_G1 | 5004 2C00h |
EPWM2_G2 | 5008 2C00h |
EPWM2_G3 | 500C 2C00h |
EPWM3_G0 | 5000 3C00h |
EPWM3_G1 | 5004 3C00h |
EPWM3_G2 | 5008 3C00h |
EPWM3_G3 | 500C 3C00h |
EPWM4_G0 | 5000 4C00h |
EPWM4_G1 | 5004 4C00h |
EPWM4_G2 | 5008 4C00h |
EPWM4_G3 | 500C 4C00h |
EPWM5_G0 | 5000 5C00h |
EPWM5_G1 | 5004 5C00h |
EPWM5_G2 | 5008 5C00h |
EPWM5_G3 | 500C 5C00h |
EPWM6_G0 | 5000 6C00h |
EPWM6_G1 | 5004 6C00h |
EPWM6_G2 | 5008 6C00h |
EPWM6_G3 | 500C 6C00h |
EPWM7_G0 | 5000 7C00h |
EPWM7_G1 | 5004 7C00h |
EPWM7_G2 | 5008 7C00h |
EPWM7_G3 | 500C 7C00h |
EPWM8_G0 | 5000 8C00h |
EPWM8_G1 | 5004 8C00h |
EPWM8_G2 | 5008 8C00h |
EPWM8_G3 | 500C 8C00h |
EPWM9_G0 | 5000 9C00h |
EPWM9_G1 | 5004 9C00h |
EPWM9_G2 | 5008 9C00h |
EPWM9_G3 | 500C 9C00h |
EPWM10_G0 | 5000 AC00h |
EPWM10_G1 | 5004 AC00h |
EPWM10_G2 | 5008 AC00h |
EPWM10_G3 | 500C AC00h |
EPWM11_G0 | 5000 BC00h |
EPWM11_G1 | 5004 BC00h |
EPWM11_G2 | 5008 BC00h |
EPWM11_G3 | 500C BC00h |
EPWM12_G0 | 5000 CC00h |
EPWM12_G1 | 5004 CC00h |
EPWM12_G2 | 5008 CC00h |
EPWM12_G3 | 500C CC00h |
EPWM13_G0 | 5000 DC00h |
EPWM13_G1 | 5004 DC00h |
EPWM13_G2 | 5008 DC00h |
EPWM13_G3 | 500C DC00h |
EPWM14_G0 | 5000 EC00h |
EPWM14_G1 | 5004 EC00h |
EPWM14_G2 | 5008 EC00h |
EPWM14_G3 | 500C EC00h |
EPWM15_G0 | 5000 FC00h |
EPWM15_G1 | 5004 FC00h |
EPWM15_G2 | 5008 FC00h |
EPWM15_G3 | 500C FC00h |
EPWM16_G0 | 5001 0C00h |
EPWM16_G1 | 5005 0C00h |
EPWM16_G2 | 5009 0C00h |
EPWM16_G3 | 500D 0C00h |
EPWM17_G0 | 5001 1C00h |
EPWM17_G1 | 5005 1C00h |
EPWM17_G2 | 5009 1C00h |
EPWM17_G3 | 500D 1C00h |
EPWM18_G0 | 5001 2C00h |
EPWM18_G1 | 5005 2C00h |
EPWM18_G2 | 5009 2C00h |
EPWM18_G3 | 500D 2C00h |
EPWM19_G0 | 5001 3C00h |
EPWM19_G1 | 5005 3C00h |
EPWM19_G2 | 5009 3C00h |
EPWM19_G3 | 500D 3C00h |
EPWM20_G0 | 5001 4C00h |
EPWM20_G1 | 5005 4C00h |
EPWM20_G2 | 5009 4C00h |
EPWM20_G3 | 500D 4C00h |
EPWM21_G0 | 5001 5C00h |
EPWM21_G1 | 5005 5C00h |
EPWM21_G2 | 5009 5C00h |
EPWM21_G3 | 500D 5C00h |
EPWM22_G0 | 5001 6C00h |
EPWM22_G1 | 5005 6C00h |
EPWM22_G2 | 5009 6C00h |
EPWM22_G3 | 500D 6C00h |
EPWM23_G0 | 5001 7C00h |
EPWM23_G1 | 5005 7C00h |
EPWM23_G2 | 5009 7C00h |
EPWM23_G3 | 500D 7C00h |
EPWM24_G0 | 5001 8C00h |
EPWM24_G1 | 5005 8C00h |
EPWM24_G2 | 5009 8C00h |
EPWM24_G3 | 500D 8C00h |
EPWM25_G0 | 5001 9C00h |
EPWM25_G1 | 5005 9C00h |
EPWM25_G2 | 5009 9C00h |
EPWM25_G3 | 500D 9C00h |
EPWM26_G0 | 5001 AC00h |
EPWM26_G1 | 5005 AC00h |
EPWM26_G2 | 5009 AC00h |
EPWM26_G3 | 500D AC00h |
EPWM27_G0 | 5001 BC00h |
EPWM27_G1 | 5005 BC00h |
EPWM27_G2 | 5009 BC00h |
EPWM27_G3 | 500D BC00h |
EPWM28_G0 | 5001 CC00h |
EPWM28_G1 | 5005 CC00h |
EPWM28_G2 | 5009 CC00h |
EPWM28_G3 | 500D CC00h |
EPWM29_G0 | 5001 DC00h |
EPWM29_G1 | 5005 DC00h |
EPWM29_G2 | 5009 DC00h |
EPWM29_G3 | 500D DC00h |
EPWM30_G0 | 5001 EC00h |
EPWM30_G1 | 5005 EC00h |
EPWM30_G2 | 5009 EC00h |
EPWM30_G3 | 500D EC00h |
EPWM31_G0 | 5001 FC00h |
EPWM31_G1 | 5005 FC00h |
EPWM31_G2 | 5009 FC00h |
EPWM31_G3 | 500D FC00h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
RESERVED_4 | POLSELB | ||||||
R | R/W | ||||||
0h | 0h | ||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
SELB | SELBLOCKB | INVERTB | RESERVED_3 | ENABLEB | |||
R/W | R/W | R/W | R | R/W | |||
0h | 0h | 0h | 0h | 0h | |||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RESERVED_2 | POLSELA | ||||||
R | R/W | ||||||
0h | 0h | ||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
SELA | SELBLOCKA | INVERTA | RESERVED_1 | ENABLEA | |||
R/W | R/W | R/W | R | R/W | |||
0h | 0h | 0h | 0h | 0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:25 | RESERVED_4 | R | 0h | Reserved |
24 | POLSELB | R/W | 0h | Select signal for the AND OR logic of BLOCKB [output of SELBLOCKB mux] and PWMB signals 0 : Select BLOCKB is inverted and ANDed with PWMB. 1 : Select BLOCKB is Ored with PWMB. |
23:20 | SELB | R/W | 0h | PWMB min dead band reference 0x0 : DEPWMB 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR |
19 | SELBLOCKB | R/W | 0h | 0 : Select BLOCKB as the blocking signal on PWMB. 1 : Select BLOCKA as the blocking signal on PWMB. |
18 | INVERTB | R/W | 0h | 0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMB. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMB. |
17 | RESERVED_3 | R | 0h | Reserved |
16 | ENABLEB | R/W | 0h | 0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled |
15:9 | RESERVED_2 | R | 0h | Reserved |
8 | POLSELA | R/W | 0h | Select signal for the AND OR logic of BLOCKA [output of SELBLOCKA mux] and PWMA signals 0 : Select BLOCKA is inverted and ANDed with PWMA. 1 : Select BLOCKA is Ored with PWMA. |
7:4 | SELA | R/W | 0h | PWMA min dead band reference 0x0 : DEPWMA 0x1 : Output 1 from PWMXBAR 0x2 : Output 2 from PWMXBAR . . 0xf : Output 15 from PWMXBAR |
3 | SELBLOCKA | R/W | 0h | 0 : Select BLOCKA as the blocking signal on PWMA. 1 : Select BLOCKB as the blocking signal on PWMB. |
2 | INVERTA | R/W | 0h | 0 : No inversion on the selected reference signal which is used in the min deadband logic on PWMA. 1 : Invert the selected reference signal which is used in the min deadband logic on PWMA. |
1 | RESERVED_1 | R | 0h | Reserved |
0 | ENABLEA | R/W | 0h | 0 : Minimum dead band logic is disabled 1 : Minimum dead band logic is enabled |