SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Minimum dead band delay register.
Return to Summary Table
Instance Name | Physical Address |
---|---|
EPWM0_G0 | 5000 0C04h |
EPWM0_G1 | 5004 0C04h |
EPWM0_G2 | 5008 0C04h |
EPWM0_G3 | 500C 0C04h |
EPWM1_G0 | 5000 1C04h |
EPWM1_G1 | 5004 1C04h |
EPWM1_G2 | 5008 1C04h |
EPWM1_G3 | 500C 1C04h |
EPWM2_G0 | 5000 2C04h |
EPWM2_G1 | 5004 2C04h |
EPWM2_G2 | 5008 2C04h |
EPWM2_G3 | 500C 2C04h |
EPWM3_G0 | 5000 3C04h |
EPWM3_G1 | 5004 3C04h |
EPWM3_G2 | 5008 3C04h |
EPWM3_G3 | 500C 3C04h |
EPWM4_G0 | 5000 4C04h |
EPWM4_G1 | 5004 4C04h |
EPWM4_G2 | 5008 4C04h |
EPWM4_G3 | 500C 4C04h |
EPWM5_G0 | 5000 5C04h |
EPWM5_G1 | 5004 5C04h |
EPWM5_G2 | 5008 5C04h |
EPWM5_G3 | 500C 5C04h |
EPWM6_G0 | 5000 6C04h |
EPWM6_G1 | 5004 6C04h |
EPWM6_G2 | 5008 6C04h |
EPWM6_G3 | 500C 6C04h |
EPWM7_G0 | 5000 7C04h |
EPWM7_G1 | 5004 7C04h |
EPWM7_G2 | 5008 7C04h |
EPWM7_G3 | 500C 7C04h |
EPWM8_G0 | 5000 8C04h |
EPWM8_G1 | 5004 8C04h |
EPWM8_G2 | 5008 8C04h |
EPWM8_G3 | 500C 8C04h |
EPWM9_G0 | 5000 9C04h |
EPWM9_G1 | 5004 9C04h |
EPWM9_G2 | 5008 9C04h |
EPWM9_G3 | 500C 9C04h |
EPWM10_G0 | 5000 AC04h |
EPWM10_G1 | 5004 AC04h |
EPWM10_G2 | 5008 AC04h |
EPWM10_G3 | 500C AC04h |
EPWM11_G0 | 5000 BC04h |
EPWM11_G1 | 5004 BC04h |
EPWM11_G2 | 5008 BC04h |
EPWM11_G3 | 500C BC04h |
EPWM12_G0 | 5000 CC04h |
EPWM12_G1 | 5004 CC04h |
EPWM12_G2 | 5008 CC04h |
EPWM12_G3 | 500C CC04h |
EPWM13_G0 | 5000 DC04h |
EPWM13_G1 | 5004 DC04h |
EPWM13_G2 | 5008 DC04h |
EPWM13_G3 | 500C DC04h |
EPWM14_G0 | 5000 EC04h |
EPWM14_G1 | 5004 EC04h |
EPWM14_G2 | 5008 EC04h |
EPWM14_G3 | 500C EC04h |
EPWM15_G0 | 5000 FC04h |
EPWM15_G1 | 5004 FC04h |
EPWM15_G2 | 5008 FC04h |
EPWM15_G3 | 500C FC04h |
EPWM16_G0 | 5001 0C04h |
EPWM16_G1 | 5005 0C04h |
EPWM16_G2 | 5009 0C04h |
EPWM16_G3 | 500D 0C04h |
EPWM17_G0 | 5001 1C04h |
EPWM17_G1 | 5005 1C04h |
EPWM17_G2 | 5009 1C04h |
EPWM17_G3 | 500D 1C04h |
EPWM18_G0 | 5001 2C04h |
EPWM18_G1 | 5005 2C04h |
EPWM18_G2 | 5009 2C04h |
EPWM18_G3 | 500D 2C04h |
EPWM19_G0 | 5001 3C04h |
EPWM19_G1 | 5005 3C04h |
EPWM19_G2 | 5009 3C04h |
EPWM19_G3 | 500D 3C04h |
EPWM20_G0 | 5001 4C04h |
EPWM20_G1 | 5005 4C04h |
EPWM20_G2 | 5009 4C04h |
EPWM20_G3 | 500D 4C04h |
EPWM21_G0 | 5001 5C04h |
EPWM21_G1 | 5005 5C04h |
EPWM21_G2 | 5009 5C04h |
EPWM21_G3 | 500D 5C04h |
EPWM22_G0 | 5001 6C04h |
EPWM22_G1 | 5005 6C04h |
EPWM22_G2 | 5009 6C04h |
EPWM22_G3 | 500D 6C04h |
EPWM23_G0 | 5001 7C04h |
EPWM23_G1 | 5005 7C04h |
EPWM23_G2 | 5009 7C04h |
EPWM23_G3 | 500D 7C04h |
EPWM24_G0 | 5001 8C04h |
EPWM24_G1 | 5005 8C04h |
EPWM24_G2 | 5009 8C04h |
EPWM24_G3 | 500D 8C04h |
EPWM25_G0 | 5001 9C04h |
EPWM25_G1 | 5005 9C04h |
EPWM25_G2 | 5009 9C04h |
EPWM25_G3 | 500D 9C04h |
EPWM26_G0 | 5001 AC04h |
EPWM26_G1 | 5005 AC04h |
EPWM26_G2 | 5009 AC04h |
EPWM26_G3 | 500D AC04h |
EPWM27_G0 | 5001 BC04h |
EPWM27_G1 | 5005 BC04h |
EPWM27_G2 | 5009 BC04h |
EPWM27_G3 | 500D BC04h |
EPWM28_G0 | 5001 CC04h |
EPWM28_G1 | 5005 CC04h |
EPWM28_G2 | 5009 CC04h |
EPWM28_G3 | 500D CC04h |
EPWM29_G0 | 5001 DC04h |
EPWM29_G1 | 5005 DC04h |
EPWM29_G2 | 5009 DC04h |
EPWM29_G3 | 500D DC04h |
EPWM30_G0 | 5001 EC04h |
EPWM30_G1 | 5005 EC04h |
EPWM30_G2 | 5009 EC04h |
EPWM30_G3 | 500D EC04h |
EPWM31_G0 | 5001 FC04h |
EPWM31_G1 | 5005 FC04h |
EPWM31_G2 | 5009 FC04h |
EPWM31_G3 | 500D FC04h |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 |
DELAYB | |||||||
R/W | |||||||
0h | |||||||
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
DELAYB | |||||||
R/W | |||||||
0h | |||||||
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
DELAYA | |||||||
R/W | |||||||
0h | |||||||
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
DELAYA | |||||||
R/W | |||||||
0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
31:16 | DELAYB | R/W | 0h | Minimum dead band delay on PWMB in terms of SYSCLK cycles. For delay value of 0, user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied. |
15:0 | DELAYA | R/W | 0h | Minimum dead band delay on PWMA in terms of SYSCLK cycles. For delay value of 0, user should configure MINDBCFG[ENABLEA/B] = '0'. If MINDBCFG[ENABLEA/B] = '1' and MINDBDLY[DELAYA/B]='0' then delay is '1' cycle is applied. |