SPRUJ60A April   2024  – October 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Feature Differences Between F280013x/15x and F28P55x
    1. 1.1 F280013x/15x and F28P55x Feature Comparison
  5. 2PCB Hardware Changes
    1. 2.1 PCB Hardware Changes for the 80-Pin PN/PNA, 64-Pin PM Packages
    2. 2.2 80-Pin PNA, 64-Pin PM Migration Between F280013x/15x and F28P55x For New and Existing PCB
  6. 3Feature Differences for System Consideration
    1. 3.1 New Features in F28P55x
      1. 3.1.1  Advance Encryption Standard (AES)
      2. 3.1.2  Universal Serial Bus (USB)
      3. 3.1.3  Configurable Logic Block (CLB)
      4. 3.1.4  Live Firmware Update (LFU)
      5. 3.1.5  Programmable Gain Amplifier (PGA)
      6. 3.1.6  ERAD
      7. 3.1.7  FSI
      8. 3.1.8  5V Failsafe IOs
      9. 3.1.9  Flash Write Protection
      10. 3.1.10 Neural-Network Processing Unit (NPU)
    2. 3.2 Communication Module Changes
    3. 3.3 Control Module Changes
    4. 3.4 Analog Module Differences
    5. 3.5 Other Device Changes
      1. 3.5.1 PLL
      2. 3.5.2 PIE Channel Mapping
      3. 3.5.3 Bootrom
    6. 3.6 Power Management
      1. 3.6.1 LDO/VREG
      2. 3.6.2 POR/BOR
      3. 3.6.3 Power Consumption
    7. 3.7 Memory Module Changes
    8. 3.8 GPIO Multiplexing Changes
    9. 3.9 Analog Multiplexing Changes
  7. 4Application Code Migration From F280013x/15x to F28P55x
    1. 4.1 C2000Ware Header Files
    2. 4.2 Linker Command Files
    3. 4.3 C2000Ware Examples
  8. 5Specific Use Cases Related to F28P55x New Features
    1. 5.1 AES
    2. 5.2 PGA
    3. 5.3 USB
  9. 6EABI Support
    1. 6.1 Flash API
  10. 7References
  11. 8Revision History

3.1.6 ERAD

The ERAD module is shown in Figure 3-1.

The ERAD enhances the debug and system analysis capabilities of the device external to the CPU. The C28x CPU alone has two analysis resources; Analysis Unit 1 (AU1) and Analysis Unit 2 (AU2). The first analysis unit counts events or monitors address buses. The second analysis unit monitors address and data buses. The two analysis units can be configured for hardware breakpoints or hardware watch points, and additionally the first analysis unit can be configured as a benchmark counter or event counter. The ERAD module further expands this capability to provide additional hardware breakpoints, hardware watch points, and counters for profiling, as well as other advanced features. The ERAD module can be utilized by the debugger, and also by the application software. For many real-time systems, it is not always possible to connect a debugger and perform an intrusive debug. Under these situations, the user's code has the ability to set up and control the ERAD module in order to debug and profile the system without disturbing the end application.

The ERAD module consists of eight enhanced bus comparator (EBC) units and four system event counter (SEC) units. The EBC units monitor buses and generate output events. The SEC units can be used with EBC units to profile and analyze the system. These units are described in detail in the following sections.

ERAD Overview Figure 3-1 ERAD Overview