SPRUJ85 April   2024

ADVANCE INFORMATION  

  1.   1
  2.   Description
  3.   Key Features
  4. 1LaunchPad Module Overview
    1. 2.1 Introduction
    2. 2.2 Preface: Read This First
      1. 2.2.1 If You Need Assistance
      2. 2.2.2 Important Usage Notes
    3. 2.3 Kit Contents
    4. 2.4 Device Information
      1. 2.4.1 System Architecture Overview
      2. 2.4.2 Security
      3. 2.4.3 Compliance
      4. 2.4.4 BoosterPacks
      5. 2.4.5 Component Identification
  5. 2Hardware Description
    1. 3.1  Board Setup
      1. 3.1.1 Power Requirements
        1. 3.1.1.1 Power Input Using USB Type-C Connector
        2. 3.1.1.2 Power Status LEDs
        3. 3.1.1.3 Power Tree
      2. 3.1.2 Push Buttons
      3. 3.1.3 Boot mode Selection
      4. 3.1.4 IO Expander
    2. 3.2  Functional Block Diagram
    3. 3.3  GPIO Mapping
    4. 3.4  Reset
    5. 3.5  Clock
    6. 3.6  Memory Interface
      1. 3.6.1 OSPI
      2. 3.6.2 Board ID EEPROM
    7. 3.7  Ethernet Interface
      1. 3.7.1 Ethernet PHY #1 - CPSW RGMII/ICSSM
      2. 3.7.2 Ethernet PHY #2 - CPSW RGMII/ICSSM
      3. 3.7.3 LED Indication in RJ45 Connector
    8. 3.8  I2C
    9. 3.9  Industrial Application LEDs
    10. 3.10 SPI
    11. 3.11 UART
    12. 3.12 MCAN
    13. 3.13 FSI
    14. 3.14 JTAG
    15. 3.15 TIVA and Test Automation Header
    16. 3.16 LIN
    17. 3.17 MMC
    18. 3.18 ADC and DAC
    19. 3.19 EQEP and SDFM
    20. 3.20 EPWM
    21. 3.21 BoosterPack Headers
    22. 3.22 Pinmux Mapping
  6. 3Additional Information
    1.     Trademarks
    2. 4.1 Sitara MCU+ Academy
  7. 4References
    1. 5.1 Reference Documents
    2. 5.2 Other TI Components Used in This Design
  8. 5Revision History

2.7.2 Ethernet PHY #2 - CPSW RGMII/ICSSM

Note: The PRU internal pinmux mapping provided in the TRM is part of the original hardware definition of the PRU. However, due to the flexibility provided by the IP and associated firmware configurations, this is not necessarily a hard requirement. The first PRU implementation for AM65x had the MII TX pins swapped during initial SOC integration and this convention was maintained for subsequent PRU revisions to enable firmware reuse. To make use of the SDK firmware, use the SYSCONFIG generated PRU pin mapping.

The AM263Px LaunchPad utilizes a 48-pin Ethernet PHY (DP83869HMRGZT) connected to either CPSW RGMII or one on-die Programmable Real-time Unit and Industrial Communication Sub System (PRU-ICSS). The RGMII CPSW port and ICSSM are internally pinmuxed on the AM263Px SoC. For more information on the internal muxing of signals refer to Pinmux Mapping. The PHY is configured to advertise 1-Gb operation. The Ethernet data signals of the PHY are terminated to an RJ45 connector. The RJ45 connector is used on the board for Ethernet 10/100/1000Mbps connectivity with integrated magnetics and LEDs for link and activity indication.

GUID-20240416-SS0I-87WB-F61Z-KNVFTVLHFDPQ-low.pngFigure 2-16 Ethernet PHY #2

The Ethernet PHY requires three separate power sources. VDDIO is the 3.3V, system generated supply. There are dedicated LDO's for the 1.1V and 2.5V supplies for the Ethernet PHY.

There are series termination resistors on the transmit clock and data signals located near the SoC. There are series termination resistors on the receive clock and data signals near the Ethernet PHY.

The MDIO signal from the SoC to the PHY require 1.5kΩ pullup resistors to the 3.3V system supply voltage for proper operation. There is an analog switch (TS5A23159DGSR) that selects between the CPSW MDIO/MDC and the ICSSM MDIO/MDC signals to be routed to the Ethernet PHY.

AM263Px internal Pinmux is used to select between CPSW RGMII and ICSSM signals. The signals are then routed to a 1:2 mux (TS3DDR3812RUAR) that selects between mapping the signals to the Ethernet PHY or the BP headers in the case that the PRU GPIO signals are being used in a BoosterPack application. There is an AM263Px SoC GPIO select signal that drives the 1:2 mux.

Table 2-10 Ethernet PHY #2 CPSW/ICSSM Select
PRU_MUX_SELConditionFunction of Mux
LOWEthernet PHY SelectedPort A ↔ Port B
HIGHBoosterPack header SelectedPort A ↔ Port C

The reset input for the Ethernet PHY is controlled by the WARMRESET AM263Px SoC output signal.

The Ethernet PHY uses many functional pins as strap option to place the device into specific modes of operation.

Table 2-11 Ethernet PHY #2 Strapping Resistors
Functional PinDefault ModeMode in LPFunction
RX_D000PHY address: 1100
RX_D103
JTAG_TDO/GPIO_100RGMII to Copper
RX_D300
RX_D200
LED_000Auto-negotiation, 1000/100/10 advertised, auto MDI-X
RX_ER00
LED_200
RX_DV00Port Mirroring Disabled
Note: Each strap pin has an internal pull down resistance of 2.49kΩ
Note: RX_D0 and RX_D1 are on a 4-level strap resistor mode scheme. All other signals are 2-level strap resistor modes.