SPRUJB1 December   2023 AM68 , AM68A , AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1

 

  1.   1
  2. 1Abstract
  3.   Trademarks
  4. 2Contributions to Power
  5. 3How to Use the Tool
    1. 3.1 Use Case
  6. 4Results Sheet
    1. 4.1 Some Specific Pre-loaded Use Case Results
      1. 4.1.1 ARM Only (x4)
      2. 4.1.2 Superset
      3. 4.1.3 Compute
  7. 5Revision History

4.1.1 ARM Only (x4)

A minimum use case for this class of processors relies upon using the A72 cores and the PCIe and ethernet switch; in this case, the A72 cores are reduced from 2GHz to 1GHz.

In this configuration, many of the power domains are disabled.

Table 4-3 ARM-only Power Domain States
PD State
GP_CORE_CTL_wkup ON
GP_Core_CTL (CC) ON
GP_Core_CTL ON
PD_Pulsar_MCU ON
PD_C7_0 OFF
PD_C7_1 OFF
PD_A72_Cluster_0 ON
PD_A72_0 ON
PD_A72_1 ON
PD_A72_Cluster_1 OFF
PD_A72_4 OFF
PD_A72_5 OFF
PD_GPUCOM OFF
PD_C7_2 OFF
PD_C7_3 OFF
PD_Pulsar_0 OFF
PD_decode OFF
PD_Pulsar_1 OFF
PD_DMPAC OFF
PD_VPAC OFF
PD_A72_2 ON
PD_A72_3 ON
PD_A72_6 OFF
PD_A72_7 OFF
PD_VPAC2 OFF
PD_encode2 OFF
PD_Pulsar_2 OFF

The device loading is shown in the following table.

Table 4-4 ARM-only Device Configuration
Tj 125
VDD_CORE_SRAM_Voltage 0.85
VDD_CORE_Voltage 0.8
VDD_CPU_SRAM_Voltage 0.85
VDD_CPU_Voltage 0.76
VDD_MCU_SRAM_Voltage 0.85
VDD_MCU_Voltage 0.85
Process_Corner strong
UC_Description
A72 CPU 70% 1000
A72 CPU 70% 1000
A72 CPU 70% 1000
A72 CPU 70% 1000
A72 CPU 0% 1000
A72 CPU 0% 1000
A72 CPU 0% 1000
A72 CPU 0% 1000
Pulsar Main 0% 1000
Pulsar Main 0% 1000
Pulsar Main 0% 1000
C711 512k 1.1 0% 1000
MMA2p1 0% 1000
C711 512k 1.1 0% 1000
MMA2p1 0% 1000
C711 512k 1.1 0% 1000
MMA2p1 0% 1000
C711 512k 1.1 0% 1000
MMA2p1 0% 1000
SMS 10% 333
Pulsar MCU 50% 1000
DSS7L_eDP_DSI 0% 600
GPU 0% 800
CSI_3RX_2TX 0% 720
DPHY 1.2 RX - 4L 0% upls
DPHY 1.2 RX - 4L 0% upls
DPHY 1.2 RX - 4L 0% upls
DPHY 1.2 TX - 4L 0% upls
DPHY 1.2 TX - 4L 0% upls
DMPAC 0% 480
VPAC3 0% 720
VPAC3 0% 720
WAVE521CL Video Codec 0% 600
WAVE521CL Video Codec 0% 600
CPSW2X eAVB 0%
CPSW9x eAVB 23%
PCIE_G3 4L 0%
PCIE_G3 4L 20%
PCIE_G3 4L 0%
PCIE_G3 4L 0%
Hyperlink x2 0%
USB3P0TCx1 0%
EMMC 4 0%
SDIO 1 bit 0% unused
EMMC 8 20%
Arasan HS400 8 bit 20% hs400
UFSHCI21 0%
MPHY - 2L 0% sleep
DDR 0 35% 1067
LPDDR4-32 PHY 4267 39% lpddr4_4267_32
DDR 1 35% 1067
LPDDR4-32 PHY 4267 39% lpddr4_4267_32
DDR 2 0% 1067
LPDDR4-32 PHY 4267 0% sleep
DDR 3 0% 1067
LPDDR4-32 PHY 4267 0% sleep
SerDes 10G Common 100% 1pll
Lane 0 20% 8g
Lane 1 20% 8g
Lane 2 20% 8g
Lane 3 20% 8g
SerDes 10G Common 100% 2pll
Lane 0 50% 5g
Lane 1 50% 5g
Lane 2 50% 1g
Lane 3 50% 1g
SerDes 10G Common 100% 1pll
Lane 0 50% 1g
Lane 1 50% 1g
Lane 2 50% 1g
Lane 3 50% 1g
SerDes 10G Common 0% suspend
Lane 0 0% disable
Lane 1 0% disable
Lane 2 0% disable
Lane 3 0% disable

The thermal power for the device is shown in the following table.

Table 4-5 ARM-only Thermal Power
Tj Leakage [mW] Dynamic [mW] Total [mW]
125 9283 5698 14981
120 8247 5698 13945
115 7276 5698 12974
110 6427 5698 12125
105 5649 5698 11347
100 4955 5698 10653
95 4347 5698 10045
90 3808 5698 9506
85 3330 5698 9028
80 2894 5698 8592
75 2519 5698 8217
50 1228 5698 6926
25 596 5698 6294
0 293 5698 5991
-20 193 5698 5891
-40 147 5698 5845