SPRUJB1 December   2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1

 

  1.   1
  2. 1Abstract
  3.   Trademarks
  4. 2Contributions to Power
  5. 3How to Use the Tool
    1. 3.1 Use Case
  6. 4Results Sheet
    1. 4.1 Some Specific Pre-loaded Use Case Results
      1. 4.1.1 ARM Only (x4)
      2. 4.1.2 Superset
      3. 4.1.3 Compute
  7. 5Revision History

4.1.2 Superset

On the other end of the spectrum is a superset use case in which A72s, Pulsars, C71x and MMAs, GPU, DMPAC and VPAC are effectively maximized. In this example, the SerDes is also loaded.

In this configuration, none of the power domains are disabled.

Table 4-6 Superset Power Domain States
PD State
GP_CORE_CTL_wkup ON
GP_Core_CTL (CC) ON
GP_Core_CTL ON
PD_Pulsar_MCU ON
PD_C7_0 ON
PD_C7_1 ON
PD_A72_Cluster_0 ON
PD_A72_0 ON
PD_A72_1 ON
PD_A72_Cluster_1 ON
PD_A72_4 ON
PD_A72_5 ON
PD_GPUCOM ON
PD_C7_2 ON
PD_C7_3 ON
PD_Pulsar_0 ON
PD_decode ON
PD_Pulsar_1 ON
PD_DMPAC ON
PD_VPAC ON
PD_A72_2 ON
PD_A72_3 ON
PD_A72_6 ON
PD_A72_7 ON
PD_VPAC2 ON
PD_encode2 ON
PD_Pulsar_2 ON

The device loading is shown in the following table.

Table 4-7 Superset Device Configuration
Tj 125
VDD_CORE_SRAM_Voltage 0.85
VDD_CORE_Voltage 0.8
VDD_CPU_SRAM_Voltage 0.85
VDD_CPU_Voltage 0.76
VDD_MCU_SRAM_Voltage 0.85
VDD_MCU_Voltage 0.8
Process_Corner Strong
UC_Description
A72 CPU 90% 2000
A72 CPU 90% 2000
A72 CPU 90% 2000
A72 CPU 90% 2000
A72 CPU 90% 2000
A72 CPU 90% 2000
A72 CPU 90% 2000
A72 CPU 10% 2000
Pulsar Main 80% 1000
Pulsar Main 80% 1000
Pulsar Main 80% 1000
C711 512k 1.1 0% 1000
MMA2p1 100% 1000
C711 512k 1.1 0% 1000
MMA2p1 100% 1000
C711 512k 1.1 0% 1000
MMA2p1 100% 1000
C711 512k 1.1 20% 1000
MMA2p1 80% 1000
SMS 10% 333
Pulsar MCU 80% 1000
DSS7L_eDP_DSI 63% 600
GPU 100% 800
CSI_3RX_2TX 64% 720
DPHY 1.2 RX - 4L 80% 2p5g4l
DPHY 1.2 RX - 4L 80% 2p5g4l
DPHY 1.2 RX - 4L 80% 2p5g4l
DPHY 1.2 TX - 4L 80% 2p5g4l
DPHY 1.2 TX - 4L 0% upls
DMPAC 79% 480
VPAC3 72% 720
VPAC3 83% 720
WAVE521CL Video Codec 75% 600
WAVE521CL Video Codec 75% 600
CPSW2X eAVB 100%
CPSW9x eAVB 50%
PCIE_G3 4L 80%
PCIE_G3 4L 80%
PCIE_G3 4L 0%
PCIE_G3 4L 0%
Hyperlink x2 0%
USB3P0TCx1 80%
EMMC 4 0%
SDIO 1 bit 0% unused
EMMC 8 50%
Arasan HS400 8 bit 50% hs400
UFSHCI21 0%
MPHY - 2L 0% sleep
DDR 0 40% 1067
LPDDR4-32 PHY 4267 44% lpddr4_4267_32
DDR 1 40% 1067
LPDDR4-32 PHY 4267 44% lpddr4_4267_32
DDR 2 40% 1067
LPDDR4-32 PHY 4267 44% lpddr4_4267_32
DDR 3 40% 1067
LPDDR4-32 PHY 4267 44% lpddr4_4267_32
SerDes 10G Common 100% 2pll
Lane 0 100% 8g
Lane 1 100% 8g
Lane 2 0% disable
Lane 3 100% 5g
SerDes 10G Common 100% 1pll
Lane 0 100% 8g
Lane 1 100% 8g
Lane 2 100% 8g
Lane 3 100% 8g
SerDes 10G Common 100% 2pll
Lane 0 100% 10g
Lane 1 100% 3g
Lane 2 100% 3g
Lane 3 100% 3g
SerDes 10G Common 100% 1pll
Lane 0 66% 5g
Lane 1 66% 5g
Lane 2 66% 5g
Lane 3 66% 5g

The thermal power for the device is shown in the following table.

Table 4-8 Superset Thermal Power
Tj [C] Leakage Power [mW] Dynamic Power [mW] Total Power [mW]
125 13910 29046 42956
120 12305 29046 41351
115 10853 29046 39899
110 9554 29046 38600
105 8404 29046 37450
100 7376 29046 36422
95 6440 29046 35486
90 5622 29046 34668
85 4894 29046 33940
80 4251 29046 33297
75 3690 29046 32736
50 1752 29046 30798
25 807 29046 29853
0 381 29046 29427
-20 228 29046 29274
-40 161 29046 29207