SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The TXx_EMPTY event is activated when a channel is enabled and its MCSPI_TXi register is empty (transient event). Enabling a channel automatically triggers this event, except in controller receive-only mode (see Section 12.1.3.4.3.4, Controller Receive-Only Mode). When the FIFO buffer is enabled (the MCSPI_CHiCONF[27] FFEW bit is set to 1), the MCSPI_IRQSTATUS TXi_EMPTY bit is set as soon as there is enough space in the buffer to write a number of bytes defined by the MCSPI_XFERLEVEL[5-0] AEL bit field.
The MCSPI_TXi register must be loaded with data to remove the source of the interrupt; the MCSPI_IRQSTATUS TXi_EMPTY interrupt status bit must be cleared for interrupt line deassertion (if the event is enabled as the interrupt source).
When FIFO is enabled, no new TXi_EMPTY event is asserted as long as the processor has not performed the number of writes into the MCSPI_TXi register defined by the MCSPI_XFERLEVEL[5-0] AEL bit field. The processor must perform the correct number of writes.