SPRUJE8 December   2024 AM2754-Q1

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Preface Read This First
      1. 1.2.1 Important Usage Notes
    3. 1.3 Kit Contents
    4. 1.4 Device Information
      1. 1.4.1 Security
    5. 1.5 Audio Expansion Connectors
  6. 2Hardware
    1. 2.1  Component Identification
    2. 2.2  Power Requirements
      1. 2.2.1 Power Input Using USB Type-C Connector
      2. 2.2.2 Power Status LEDs
      3. 2.2.3 Power Tree
      4. 2.2.4 Power Sequence
      5. 2.2.5 PMIC
    3. 2.3  Reset
    4. 2.4  Clock
    5. 2.5  Boot Mode Selection
    6. 2.6  Header Information
    7. 2.7  Push Buttons
    8. 2.8  Switches
    9. 2.9  Interfaces
      1. 2.9.1 Ethernet Interface
        1. 2.9.1.1 Ethernet Add-on Connectors
      2. 2.9.2 Audio Interfaces
        1. 2.9.2.1 Audio Clocking
        2. 2.9.2.2 McASP
        3. 2.9.2.3 MLB
    10. 2.10 AEC Mapping
      1. 2.10.1 Audio Expansion Connector 1
      2. 2.10.2 Audio Expansion Connector 2
    11. 2.11 Test Points
  7. 3Hardware Design Files
  8. 4Additional Information
    1. 4.1 If You need Assistance
    2. 4.2 Trademarks
  9. 5References
    1. 5.1 Reference Documents
    2. 5.2 Other TI Components Used This Design
  10. 6Revision History

2.3 Reset

Figure 2-8 shows the reset architecture of the AM275x EVM.

AM2754, AM2754-Q1, AM2752, AM2752-Q1 Reset Architecture Diagram Figure 2-8 Reset Architecture Diagram

The AM275x SoC has the following resets:

  • MCU_PORz is the Power-On-Reset for the AM275 SoC.
  • MCU_RESETz is the Warm Reset to AM275 SoC.
  • RESETSTATz_1V8 is the reset for the Main Domain.

AM2754, AM2754-Q1, AM2752, AM2752-Q1 MCU_PORz Reset Signal Tree Figure 2-9 MCU_PORz Reset Signal Tree

The MCU_PORz signal is driven by a 3-input AND gates that generates a power on reset to the SoC when:

  • The PMIC drives the PMIC PowerGood output signal low.
  • The 5V buck regulator outputs a low signal for the power good signal.
  • An external JTAG debugger drives the JTAG emulation reset signal low.
  • The XDS Test Automation Header outputs a logic LOW signal (TEST_MCU_PORzn).
  • The user push button (SW8) is pressed.

The MCU_PORz signal is tied to:

  • AM275x SoC PORz input

MCU_PORz is also driven LOW by populating Jumper J32.

The MCU_RESETz signal creates a warm reset to the SoC when:

  • The user push button (SW6) is pressed.
  • The Test Automation Header outputs a logic LOW signal (TEST_WARMRESETn) to a P-Channel MOSFET gate which causes V_GS of the PMOS to be less than zero and so the MCU_RESETz signal connects to the PMOS drain which is tied directly to ground.

The MCU_RESETz signal is tied to:

  • AM275x SoC MCU_RESETz input
  • Audio Expansion Connectors (1&2)

AM2754, AM2754-Q1, AM2752, AM2752-Q1 RESETSTATz Reset Signal Tree Figure 2-10 RESETSTATz Reset Signal Tree

The RESETSTATz_1V8 signal is the reset status signal for when a power-on reset or warm reset is triggered

The RESETSTATz_1V8 signal is tied to:

  1. Ethernet Expansion Connector reset (1&2)
  2. IO expander(U18) reset
  3. HYPERRAM reset
  4. OSPI reset
  5. eMMC reset
  6. MMC0 SD enable
  7. PCM reset(1&2)
  8. Audio Expansion Connector(1&2)
  9. BOOTMODE buffer output enable

The AM275x EVM also has an external interrupt to the SoC, GPIO1_23_INTn, that occurs when:

  • The user push button (SW5) is pressed.
  • The Test Automation Header outputs a logic LOW signal (TEST_GPIO1) to a P-Channel MOSFET gate which causes V_GS of the PMOS to be less than zero and so the GPIO1_23_INTn signal connects to the PMOS drain which is tied directly to ground.