SPRUJE8 December 2024 AM2754-Q1
The bootmode for the AM275x is selected by two DIP switches SW2(0:7) and SW1(8:15), or the test automation header. The test automation header uses an I2C IO expansion buffer to drive the bootmode when PORz is toggled.
SW2.3 | SW2.2 | SW2.1 | PLL REF CLK (MHz) |
---|---|---|---|
OFF | OFF | OFF | RVSD |
OFF | OFF | ON | RSVD |
OFF | ON | OFF | 24 MHz |
OFF | ON | ON | 25 MHz |
ON | OFF | OFF | 26 MHz |
ON | OFF | ON | RSVD |
ON | ON | OFF | RSVD |
ON | ON | ON | RSVD |
SW2.7 | SW2.6 | SW2.5 | SW2.4 | Primary Boot Mode Selected |
---|---|---|---|---|
OFF | OFF | OFF | OFF | Serial NAND |
OFF | OFF | OFF | ON | OSPI |
OFF | OFF | ON | OFF | QSPI |
OFF | OFF | ON | ON | SPI |
OFF | ON | OFF | OFF | RGMII1 |
OFF | ON | OFF | ON | RMII1 |
OFF | ON | ON | OFF | I2C0 |
OFF | ON | ON | ON | UART0 |
ON | OFF | OFF | OFF | MMC/SD Card |
ON | OFF | OFF | ON | eMMC |
ON | OFF | ON | OFF | USB |
ON | OFF | ON | ON | RSVD |
ON | ON | OFF | OFF | RSVD |
ON | ON | OFF | ON | Fast-xSPI |
ON | ON | ON | OFF | xSPI |
ON | ON | ON | ON | No-boot/Dev boot |
SW1.2 | SW1.1 | SW2.8 | Primary Boot Mode | |||
---|---|---|---|---|---|---|
RVSD | Read Mode2 | 0: RSVD (Read mode is taken from Read Mode 1) | Read Mode1 | 0 : OSPI/ 1-1-8 Mode (valid only when Read Mode 2 is 0) | Serial NAND | |
1: SPI/ 1-1-1 Mode (Read mode is taken from Read Mode 2 and Read Mode 1 is ignored) | 1 : QSPI/ 1-1-4 Mode (valid only when Read Mode 2 is 0) | |||||
RVSD | RSVD | Csel | 0: Chip Select 0 | OSPI | ||
1: Chip Select 1 | ||||||
RVSD | RSVD | Csel | 0: Chip Select 0 | QSPI | ||
1: Chip Select 1 | ||||||
RVSD | Mode | 0: SPI Mode 0 | Csel | 0: Chip Select 0 | SPI | |
1: SPI Mode 3 | 1: Chip Select 1 | |||||
0 | 0 | Link stat | 0: Phy scan used for speed/duplex setup | RGMII1 | ||
1: RGMII status register used for speed/duplex setup | ||||||
CLKOUT | 0: 50 MHz clock not generated on CLKOUT0 | CLK SRC | 0: External clock source | 0 | RMII1 | |
1: 50 MHz clock generated on CLKOUT0 | 1: Internal clock source | |||||
Bus reset | 0: Hung bus reset attempt after 1ms | RSVD | Addr | 0: 0x50 | I2C0 | |
1: No hung Bus reset attempted | 1: 0x51 | |||||
RSVD | RSVD | RSVD | UART0 | |||
0 | RSVD | Fs/Raw | 0: FileSystem Mode | MMC/SD Card | ||
1: Raw Mode | ||||||
RSVD | RSVD | RSVD | eMMC | |||
Core Volt | 0: 0.85V Core Voltage | Mode | 0: DFU(Device) | Lane Swap | 0: No swapping of DP/DM | USB |
1: 0.75V Core Voltage | 1: TBD | 1: DP/DM is swapped | ||||
RSVD | RSVD | RSVD | RSVD | |||
RSVD | RSVD | RSVD | RSVD | |||
RSVD | RSVD | RSVD | Fast-xSPI | |||
SFDP | 0: SFDP disabled | Read Cmd | 0: 0x0B Read Command | Mode | 0: 1S-1S-1S mode @ 50MHz | xSPI |
1: SFDP enabled | 1: 0xEE Read Command | 1:8D-8D-8D mode @ 25 MHz | ||||
RSVD | ARM/Thumb | 0: ARM mode | No/Dev | 0: Development Boot | No-boot/Dev boot | |
1: Thumb mode | 1: No Boot |
SW1.5 | SW1.4 | SW1.3 | Backup Boot Mode Selected |
---|---|---|---|
OFF | OFF | OFF | None |
OFF | OFF | ON | USB |
OFF | ON | OFF | RSVD |
OFF | ON | ON | UART |
ON | OFF | OFF | Ethernet |
ON | OFF | ON | MMC |
ON | ON | OFF | SPI |
ON | ON | ON | I2C |
SW1.6 | Backup Boot Mode | Defaulted Values for Back up Boot Mode | |
---|---|---|---|
RSVD | None | ||
Mode | 0: DFU(Device) | USB | Core Volt bit = 0 Lane Swap bit = 0 |
1: TBD | |||
RSVD | RSVD | ||
RSVD | UART | ||
IF | 0: RGMII with internal Delay | Ethernet | Link Stat bit = 0 (If RGMII) |
1: RGMII with external clock source | ClkOut bit= 0 & Clksrc bit = 1 (If RMII) |
||
0 | MMC | Mode bit = 0 | |
RSVD | SPI | Csel bit = 0 Mode = 0 |
|
RSVD | I2C | Addr = 0 Bus Rest = 0 |