SPRY344A January   2022  – March 2023 AM67 , AM67A , AM68 , AM68A , AM69 , AM69A , TDA4AEN-Q1 , TDA4AH-Q1 , TDA4AL-Q1 , TDA4AP-Q1 , TDA4APE-Q1 , TDA4VE-Q1 , TDA4VEN-Q1 , TDA4VH-Q1 , TDA4VL-Q1 , TDA4VM , TDA4VM-Q1 , TDA4VP-Q1 , TDA4VPE-Q1

 

  1.   At a glance
  2.   Authors
  3.   Introduction
  4.   Defining AI at the edge
  5.   What is an efficient edge AI system?
    1.     Selecting an SoC architecture
    2.     Programmable core types and accelerators
  6.   Designing edge AI systems with TI vision processors
    1.     Deep learning accelerator
    2.     Imaging and computer vision hardware accelerators
    3.     Smart internal bus and memory architecture
    4.     Optimized system BOM
    5.     Easy-to-use software development environment
  7.   Conclusion

Selecting an SoC architecture

There are two types of embedded processor design options: homogeneous architecture and heterogeneous architecture, usually incorporating specialized processing capabilities to handle certain tasks You should evaluate which architecture best meets the needs of your your edge AI system based on the required core types.

The goal of an edge AI system is to run AI, vision, video and other tasks on the best-suited core so that the resulting system is optimized for performance per watt and performance per TOPS per second, as well as cost, size and weight. A heterogenous architecture that has the right cores for the right task is crucial for edge AI systems.

Not all processors with heterogenous architectures are designed equally. A silicon vendor has to select the right processing functions or processes and decide whether to accelerate those functions in hardware or make them configurable or programmable. They must also pay attention to the integration of cores into a system. The bus architecture and memory subsystem must enable efficient data movement between the cores.

Vision-based edge AI systems can be ineffective if the SoC has the incorrect core types for task acceleration, or too many cores not managed efficiently, or an inefficient bus infrastructure and memory subsystem.