SPRZ375L October 2012 – June 2020 F28M36H33B2 , F28M36H53B2 , F28M36P53C2 , F28M36P63C2
Revision(s) Affected: A, B, E, F
On the revision 0 silicon, the polarity of the ALE (address latch enable) signal was active HIGH and it was not configurable. On new silicon revisions, a configuration bit (ALEHIGH) has been added in existing host bus configuration registers so that the user can configure the polarity of the ALE signal as per system requirement. Reset value of this bit is set to “1” to have the default polarity of ALE as active HIGH so that it is compatible with the revision 0 silicon (‘0’ will make it active LOW). Since this configuration field was reserved in the revision 0 silicon, if the application writes ‘0’ to this field (while configuring other bit fields in this register), there would be no issue for the revision 0 silicon, but the same code will not work on the revision A silicon. This is because ‘0’ means active LOW polarity for ALE on revision A silicon. This bit needs to be set to ‘1’ to make it work on the revision A silicon.