SPRZ375L October   2012  – June 2020 F28M36H33B2 , F28M36H53B2 , F28M36P53C2 , F28M36P63C2

 

  1.   F28M36x Concerto MCUs Silicon Errata Silicon Revisions F, E, B, A, 0
    1. 1 Introduction
    2. 2 Device and Development Support Tool Nomenclature
    3. 3 Device Markings
    4. 4 Usage Notes and Known Design Exceptions to Functional Specifications
      1. 4.1 Usage Notes
        1. 4.1.1  PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
        2. 4.1.2  FPU32 and VCU Back-to-Back Memory Accesses
        3. 4.1.3  Caution While Using Nested Interrupts
        4. 4.1.4  PBIST: PBIST Memory Test Feature is Deprecated
        5. 4.1.5  HWBIST: Cortex-M3 HWBIST Feature is Deprecated
        6. 4.1.6  HWBIST: C28x HWBIST Feature Support is Restricted to TI-Supplied Software
        7. 4.1.7  Flash Tools: Device Revision Requires a Flash Tools Update
        8. 4.1.8  EPI: New Feature Addition to EPI Module
        9. 4.1.9  EPI: ALE Signal Polarity
        10. 4.1.10 EPI: CS0/CS1 Swap
      2. 4.2 Known Design Exceptions to Functional Specifications
    5. 5 Documentation Support
  2.   Trademarks
  3.   Revision History

4.1.2 FPU32 and VCU Back-to-Back Memory Accesses

Revision(s) Affected: 0, A, B, E, F

This usage note applies when a VCU memory access and an FPU memory access occur back-to-back. There are three cases:

Case 1. Back-to-back memory reads: one read performed by a VCU instruction (VMOV32) and one read performed by an FPU32 instruction (MOV32).

If an R1 pipeline phase stall occurs during the first read, then the second read will latch the wrong data. If the first instruction is not stalled during the R1 pipeline phase, then the second read will occur properly.

The order of the instructions—FPU followed by VCU or VCU followed by FPU—does not matter. The address of the memory location accessed by either read does not matter.

Case 1 Workaround: Insert one instruction between the two back-to-back read instructions. Any instruction, except a VCU or FPU memory read, can be used.

Case 1, Example 1:

VMOV32 VR1,mem32 ; VCU memory read NOP ; Not a FPU/ VCU memory read MOV32 R0H,mem32 ; FPU memory read

Case 1, Example 2:

VMOV32 VR1,mem32 ; VCU memory read VMOV32 mem32, VR2 ; VCU memory write MOV32 R0H,mem32 ; FPU memory read

Case 2. Back-to-back memory writes: one write performed by a VCU instruction (VMOV32) and one write performed by an FPU instruction (MOV32).

If a pipeline stall occurs during the first write, then the second write can corrupt the data. If the first instruction is not stalled in the write phase, then no corruption will occur.

The order of the instructions—FPU followed by VCU or VCU followed by FPU—does not matter. The address of the memory location accessed by either write does not matter.

Case 2 Workaround: Insert two instructions between the back-to-back VCU and FPU writes. Any instructions, except VCU or FPU memory writes, can be used.

Case 2, Example 1:

VMOV32 mem32,VR0 ; VCU memory write NOP ; Not a FPU/VCU memory write NOP ; Not a FPU/VCU memory write MOV32 mem32,R3H ; FPU memory write

Case 2, Example 2:

VMOV32 mem32,VR0 ; VCU memory write VMOV32 VR1, mem32 ; VCU memory read NOP MOV32 mem32,R3H ; FPU memory write

Case 3. Back-to-back memory writes followed by a read or a memory read followed by a write. In this case, there is no interaction between the two instructions. No action is required.

Workaround: See Case 1 Workaround and Case 2 Workaround.