BCDMA |
i2431 — BCDMA: RX Channel can lockup in certain
scenarios |
YES |
Boot |
i2307 — Boot: ROM does not properly select OSPI clocking
modes based on BOOTMODE |
YES |
Boot |
i2328 — Boot: USB MSC boots intermittently |
YES |
Boot |
i2366 — Boot: ROM does not comprehend specific JEDEC SFDP features for
8D-8D-8D operation |
YES |
Boot |
i2371 — Boot: ROM code may hang in UART boot mode during data
transfer |
YES |
Boot |
i2410 — Boot: ROM may fail to boot due to i2409 |
YES |
Boot |
i2413 — Boot: HS-FS ROM boots corrupted ROM boot image |
YES |
Boot |
i2414 — Boot: Ethernet PHY Scan and Bring-Up Flow doesn't work with
PHYs that don't support Auto Negotiation |
YES |
Boot |
i2415 — Boot: UART Backup Boot Authentication Failure w/ xSPI Primary
Boot Mode |
YES |
Boot |
i2416 — Boot: FAT boot partition with ESP flag doesn't boot |
YES |
Boot |
i2417 — Boot: GPMC NAND configured to slower clock speed |
YES |
Boot |
i2418 — Boot: Secure ROM Panic due to Certificate Info not
present |
YES |
Boot |
i2419 — Boot: When disabling deskew calibration, ROM does not check if
deskew calibration was enabled |
YES |
Boot |
i2420 — Boot: XSPI Boot time is not consistent in SFDP mode |
YES |
Boot |
i2421 — Boot: fatTiny GPT handling causes data abort |
YES |
Boot |
i2422 — Boot: ROM timeout for MMCSD filesystem boot too long |
YES |
Boot |
i2423 — Boot: HS-FS ROM applies debug access restrictions to all
address space covered by the efuse controller firewall |
YES |
Boot |
i2435 — Boot: ROM timeout for eMMC boot too long |
YES |
CPSW |
i2208 —
CPSW: ALE IET Express Packet Drops |
YES |
CPSW |
i2401 — CPSW: Host Timestamps Cause CPSW Port to Lock up |
YES |
DDR |
i2232 —
DDR: Controller postpones more than allowed refreshes after
frequency change |
YES |
DDR |
i2244 —
DDR: Valid stop value must be defined for write DQ VREF
training |
YES |
DEBUG |
i2283 — Restrictions on how CP Tracer Debug Probes can be used |
YES |
DMA |
i2320 — BCDMA, PKTDMA: Descriptors and TRs required to
be returned unfragmented |
YES |
DSS |
i2097 —
DSS: Disabling a layer connected to Overlay may result in synclost
during the next frame |
YES |
ECC_AGGR |
i2049 —
ECC_AGGR: Potential IP Clockstop/Reset Sequence Hang due to Pending
ECC Aggregator Interrupts |
YES |
Internal Diagnostic
Modules |
i2103 —
Incorrect Reporting of ECC_GRP, ECC_BIT and ECC_TYPE Information for
Functional Safety Errors |
YES |
Interrupt
Aggregator |
i2196 —
IA: Potential deadlock scenarios in IA |
YES |
MCAN |
i2279 — MCAN: Specification Update for dedicated Tx
Buffers and Tx Queues configured with same Message ID |
YES |
MCAN |
i2278 — MCAN: Message Transmit order not guaranteed from
dedicated Tx Buffers configured with same Message ID |
YES |
MDIO |
i2329 — MDIO: MDIO interface corruption (CPSW and
PRU-ICSS) |
YES |
MMCSD |
i2312 — MMCSD: HS200 and SDR104 Command Timeout Window Too Small |
YES |
OSPI |
i2189 —
OSPI: Controller PHY Tuning Algorithm |
YES |
OSPI |
i2249 — OSPI: Internal PHY Loopback and Internal Pad
Loopback clocking modes with DDR timing inoperable |
YES |
OSPI |
i2383 — OSPI: 2-byte address is not supported in PHY DDR mode |
YES |
PRG |
i2253 — PRG: CTRL_MMR STAT registers are unreliable indicators of POK
threshold failure |
YES |
RAT |
i2062 —
RAT: Error Interrupt Triggered Even When Error Logging Disable Is
Set |
YES |
RESET |
i2407— RESET: MCU_RESETSTATz unreliable when MCU_RESETz is asserted low |
YES |
RTC |
i2327 — RTC: Hardware wakeup event limitation |
YES |
USART |
i2310 — USART: Erroneous clear/trigger of timeout
interrupt |
YES |
USART |
i2311 — USART Spurious DMA Interrupts |
YES |
USB |
i2134 — USB: 2.0 Compliance Receive Sensitivity Test
Limitation |
YES |
USB |
i2409 — USB: USB2 PHY locks up due to short suspend |
YES |