SPRZ487F May   2022  – December 2024 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP

 

  1.   1
  2. 1Usage Notes and Advisories Matrices
    1. 1.1 Devices Supported
  3. 2Silicon Usage Notes and Advisories
    1. 2.1 Silicon Usage Notes
      1.      i2351
      2.      i2372
      3.      i2424
    2. 2.2 Silicon Advisories
      1.      i2049
      2.      i2062
      3.      i2097
      4.      i2103
      5.      i2134
      6.      i2189
      7.      i2196
      8.      i2232
      9.      i2244
      10.      i2310
      11.      i2311
      12.      i2327
      13.      i2328
      14.      i2279
      15.      i2307
      16.      i2320
      17.      i2329
      18.      i2208
      19.      i2249
      20.      i2278
      21.      i2312
      22.      i2366
      23.      i2371
      24.      i2253
      25.      i2283
      26.      i2383
      27.      i2401
      28.      i2407
      29.      i2409
      30.      i2410
      31.      i2413
      32.      i2414
      33.      i2415
      34.      i2416
      35.      i2417
      36.      i2418
      37.      i2419
      38.      i2420
      39.      i2421
      40.      i2422
      41.      i2423
      42.      i2435
      43.      i2431
  4.   Trademarks
  5.   Revision History

i2189

OSPI: Controller PHY Tuning Algorithm

Details:

The OSPI controller uses a DQS signal to sample data when the PHY Module is enabled. However, there is an issue in the module which requires that this sample must occur within a window defined by the internal clock. Read operations are subject to external delays, which change with temperature. In order to guarantee valid reads at any temperature, a special tuning algorithm must be implemented which selects the most robust TX, RX, and Read Delay values.

Workaround(s):

The workaround for this bug is described in detail in SPRACT2. To sample data under some PVT conditions, it is necessary to increment the Read Delay field to shift the internal clock sampling window. This allows sampling of the data anywhere within the data eye. However, this has these side effects:

  1. PHY Pipeline mode must be enabled for all read operations. Because PHY Pipeline mode must be disabled for writes, reads and writes must be handled separately.
  2. Hardware polling of the busy bit is broken when the workaround is in place, so SW polling must be used instead. Writes must occur through DMA accesses, within page boundaries, to prevent interruption from either the host or the flash device. Software must poll the busy bit between page writes. Alternatively, writes can be performed in non-PHY mode with hardware polling enabled.
  3. STIG reads must be padded with extra bytes, and the received data must be right-shifted.