SPRZ487F May   2022  – December 2024 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP

 

  1.   1
  2. 1Usage Notes and Advisories Matrices
    1. 1.1 Devices Supported
  3. 2Silicon Usage Notes and Advisories
    1. 2.1 Silicon Usage Notes
      1.      i2351
      2.      i2372
      3.      i2424
    2. 2.2 Silicon Advisories
      1.      i2049
      2.      i2062
      3.      i2097
      4.      i2103
      5.      i2134
      6.      i2189
      7.      i2196
      8.      i2232
      9.      i2244
      10.      i2310
      11.      i2311
      12.      i2327
      13.      i2328
      14.      i2279
      15.      i2307
      16.      i2320
      17.      i2329
      18.      i2208
      19.      i2249
      20.      i2278
      21.      i2312
      22.      i2366
      23.      i2371
      24.      i2253
      25.      i2283
      26.      i2383
      27.      i2401
      28.      i2407
      29.      i2409
      30.      i2410
      31.      i2413
      32.      i2414
      33.      i2415
      34.      i2416
      35.      i2417
      36.      i2418
      37.      i2419
      38.      i2420
      39.      i2421
      40.      i2422
      41.      i2423
      42.      i2435
      43.      i2431
  4.   Trademarks
  5.   Revision History

i2383

OSPI: 2-byte address is not supported in PHY DDR mode

Details:

When the OSPI controller is configured for 2-byte addressing in PHY DDR Mode, an internal state machine mis-compares the number of address bytes transmitted to a value of 1 (instead of 2). This results in a state machine lockup in the address phase, rendering PHY DDR mode non-operable.

This issue does not occur when using any Tap mode or PHY SDR mode. This issue also doesn't occur when using 4 byte addressing in PHY DDR mode.

Workaround(s):

For compatible OSPI memories that have programmable address byte settings, set the amount of address bytes required from 2 to 4 on the flash. This may involve sending a specific command to change address bytes and/or writing a configuration register on the flash. Once done, update the amount of address bytes sent in the controller settings from 2 to 4.

For compatible OSPI memories that only support 2-byte addressing and cannot be re-programmed, PHY DDR mode will not be compatible with that memory. Alternative modes include:

  • PHY SDR mode
  • TAP (no-PHY) DDR mode
  • TAP (no-PHY) SDR mode