SPRZ487F May   2022  – December 2024 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP

 

  1.   1
  2. 1Usage Notes and Advisories Matrices
    1. 1.1 Devices Supported
  3. 2Silicon Usage Notes and Advisories
    1. 2.1 Silicon Usage Notes
      1.      i2351
      2.      i2372
      3.      i2424
    2. 2.2 Silicon Advisories
      1.      i2049
      2.      i2062
      3.      i2097
      4.      i2103
      5.      i2134
      6.      i2189
      7.      i2196
      8.      i2232
      9.      i2244
      10.      i2310
      11.      i2311
      12.      i2327
      13.      i2328
      14.      i2279
      15.      i2307
      16.      i2320
      17.      i2329
      18.      i2208
      19.      i2249
      20.      i2278
      21.      i2312
      22.      i2366
      23.      i2371
      24.      i2253
      25.      i2283
      26.      i2383
      27.      i2401
      28.      i2407
      29.      i2409
      30.      i2410
      31.      i2413
      32.      i2414
      33.      i2415
      34.      i2416
      35.      i2417
      36.      i2418
      37.      i2419
      38.      i2420
      39.      i2421
      40.      i2422
      41.      i2423
      42.      i2435
      43.      i2431
  4.   Trademarks
  5.   Revision History

i2232

DDR: Controller postpones more than allowed refreshes after frequency change

Details

When dynamically switching from a higher to lower clock frequency, the rolling window counters that control the postponing of refresh commands are not loaded correctly to scale to the lower clock frequency. This will result in controller postponing more refresh commands than allowed by the DRAM specification, thus violating refresh requirement for the DRAM.

Workaround

Workaround 1:Disable dynamic frequency change by programing DFS_ENABLE = 0

Workaround 2:If switching frequency, program the register field values based on the pseudo code listed below.Note that the controller requires AREF_*_THRESHOLD values to be programmed before triggering initialization. Their values cannot be changed during mission mode after initialization . Therefore, the value of these parameters must be the lowest of all values needed for every frequency change transition planned to be used.


if (old_freq/new_freq >= 7){ 
    if (PBR_EN==1) { // Per-bank refresh is enabled
        AREF_HIGH_THRESHOLD = 19
        AREF_NORM_THRESHOLD = 18
        AREF_PBR_CONT_EN_THRESHOLD = 17
        AREF_CMD_MAX_PER_TREF = 8 
    } 
    else { // Per-bank refresh is disabled
        AREF_HIGH_THRESHOLD = 18
        AREF_NORM_THRESHOLD = 17 
        // AREF_PBR_CONT_EN_THRESHOLD <=== don’t care, PBR not enabled
        AREF_CMD_MAX_PER_TREF = 8 
    }
}
else { 
    AREF_HIGH_THRESHOLD = 21 
    AREF_NORM_THRESHOLD //<=== keep AREF_NORM_THRESHOLD < AREF_HIGH_THRESHOLD
    AREF_CMD_MAX_PER_TREF = 8 
    if (PBR_EN==1) { // Per-bank refresh is enabled 
    //keep AREF_PBR_CONT_EN_THRESHOLD<AREF_NORM_THRESHOLD<AREF_HIGH_THRESHOLD
        AREF_PBR_CONT_EN_THRESHOLD
    }
}