SPRZ487F May 2022 – December 2024 AM620-Q1 , AM623 , AM625 , AM625-Q1 , AM625SIP
Boot: GPMC NAND configured to slower clock speed
When using GPMC NAND boot mode the GPMCFCLKDIVIDER field of the GPMC_CONFIG1 register bit [1:0] (i.e. GPMCFCLKDIVIDER) gets set to 1 which causes a divide by 2 for the GPMC_FCLK.
The ROM uses very conservative CONFIG timing values anyways so end result may not really adversely affect throughput.
None.