Details:

The Dual-clock Comparator module, which is used to monitor a clock frequency while comparing with a known clock reference, could stop earlier than expected, and, thus, indicating the measured clock frequency to be lower. This is due to a clock domain crossing issue causing a preset to the error detection logic to get triggered.

Workaround(s):

Work-around (1): Application code, where possible, could compare the clocks using an alternate EDCC module (Present in MSS)

Work-around (2): Multiple measurements can be taken for the same clock pairs and abnormal frequencies reported can be ignored.