Revision
History
Changes from September 1, 2022 to June 10, 2023 (from Revision C (September 2022) to Revision D (June 2023))
- Added Advisory i2151; ADC: Debounce time control
registerGo
- Added Advisory i2221; CC: Invasive and Non-Invasive debug enable
settings are reset by MCU_RESETzGo
- Added Advisory i2222; Compute Cluster: A72 Corepac unable to be
powered downGo
- Updated Description and Workaround for i2227; R5FSS: Error interrupt
CCM_COMPARE_STAT_PULSE_INTR incorrectly driven.Go
- Added Advisory i2243; PCIe: Timing requirement for disabling output refclk
during L1.2 substate is not metGo
- Added i2246; PCIe: Automatic compliance entry fails when unused SERDES lanes
are not assigned to PCIe ControllerGo
- Added Advisory i2249; OSPI: Internal PHY Loopback and Internal Pad Loopback
clocking modes with DDR timing inoperableGo
- Added Advisory i2253; PRG: CTRL_MMR STAT registers are unreliable indicators
of POK threshold failureGo
- Added Advisory i2274; DDR: Including DDR in BSCAN causes current alarm on
the DDR supplyGo
- Added Advisory i2275; DMSC Secure Boot ROM: Potential Secure Boot
vulnerability with explicit EC curve parameters in X.509 certificateGo
- Added Advisory i2283; Restrictions on how CP Tracer Debug Probes can be
usedGo
- Added Advisory i2306; ROM Code: Need to turn off internal termination
resistors in SERDESGo
- Added Advisory i2312; MMCSD: HS200 and SDR104 Command Timeout Window
Too SmallGo
- Added Advisory i2326; PCIe: MAIN_PLLx operating in fractional mode,
which is required for enabling SSC, is not compliant with PCIe Refclk jitter
limitsGo
- Added Usage Note i2351; OSPI: Controller does not support Continuous
Read mode with NAND FlashGo
- Added Advisory i2360; Boot: Ethernet RMII Boot Mode is not
supportedGo
- Added Advisory i2361; Boot: SPI and xSPI BOOTMODE Pin Mapping
changes for SR2.0Go
- Added Advisory i2362; 10-100M SGMII: Marvell PHY does not ignore the
preamble byte resulting in link failureGo
- Added Advisory i2366; Boot: ROM does not comprehend specific JEDEC
SFDP features for 8D-8D-8D operationGo
- Added Advisory i2371; Boot: ROM code may hang in UART boot mode
during data transferGo
- Added Usage Note i2372; Boot: ROM doesn't support select multi-plane
addressing schemes in Serial NAND bootGo
- Added Advisory i2383; OSPI: 2-byte address is not supported in PHY DDR
modeGo