SPRZ536B September   2022  – July 2024 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4APE-Q1 , TDA4VH-Q1 , TDA4VP-Q1 , TDA4VPE-Q1

 

  1.   1
  2. 1Modules Affected
  3. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  4. 3Silicon Revision 1.0 Usage Notes and Advisories
    1. 3.1 Silicon Revision 1.0 Usage Notes
      1.      i2134
    2. 3.2 Silicon Revision 1.0 Advisories
      1.      i2049
      2.      i2062
      3.      i2063
      4.      i2064
      5.      i2065
      6.      i2079
      7.      i2097
      8.      i2102
      9.      i2103
      10.      i2120
      11.      i2134
      12.      i2137
      13.      i2146
      14.      i2157
      15.      i2159
      16.      i2160
      17.      i2161
      18.      i2163
      19.      i2166
      20.      i2177
      21.      i2189
      22.      i2190
      23.      i2196
      24.      i2197
      25.      i2205
      26.      i2215
      27.      i2216
      28.      i2219
      29.      i2232
      30.      i2234
      31.      i2242
      32.      i2244
      33.      i2249
      34.      i2253
      35.      i2271
      36.      i2272
      37.      i2278
      38.      i2279
      39.      i2310
      40.      i2311
      41.      i2312
      42.      i2320
      43.      i2326
      44.      i2351
      45.      i2362
      46.      i2366
      47.      i2371
      48.      i2372
      49.      i2378
      50.      i2381
      51.      i2383
      52.      i2399
      53.      i2401
      54.      i2409
      55.      i2414
      56.      i2419
      57.      i2422
      58.      i2435
      59.      i2437
  5.   Trademarks
  6.   Revision History

i2079


C71x: DMA Accesses to L1D SRAM May Stall Indefinitely in the Presence of CPU Traffic in Specific Conditions

Details:

DMA reads or writes to L1D SRAM may stall indefinitely. These transactions are required to sensitize this condition:

  1. Buffer/line ‘A’ previously allocated in L1D cache.
  2. CPU reads miss L1D cache to buffer/line ’A’.
  3. Streaming engine reads to buffer/line ‘A’.
  4. DMA reads or writes to a buffer in L1D SRAM.

Note that transactions #1, #2 and #3 are to the same buffer/line, while #4 is to a different buffer/line. This can encounter a condition which causes the DMAs to stall indefinitely.

Workaround(s):

Avoid doing DMAs to buffers mapped to L1D SRAM.